Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	634415532	296112	0	0
wdog_bark_thold_rd_A	634415532	10711	0	0
wdog_bite_thold_rd_A	634415532	10175	0	0
wdog_ctrl_rd_A	634415532	9589	0	0
wdog_regwen_rd_A	634415532	11433	0	0
wkup_ctrl_rd_A	634415532	9695	0	0
wkup_thold_hi_rd_A	634415532	11575	0	0
wkup_thold_lo_rd_A	634415532	10134	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634415532	296112	0	0
T21	154321	2759	0	0
T22	343914	0	0	0
T23	8924	0	0	0
T25	17244	0	0	0
T26	195781	2027	0	0
T27	613837	0	0	0
T28	0	3183	0	0
T29	10143	0	0	0
T30	0	6605	0	0
T35	0	8124	0	0
T37	19806	0	0	0
T38	35050	0	0	0
T46	0	2788	0	0
T47	0	4333	0	0
T48	0	9102	0	0
T49	0	5359	0	0
T50	0	2208	0	0
T51	3351	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634415532	10711	0	0
T21	154321	324	0	0
T22	343914	0	0	0
T23	8924	0	0	0
T25	17244	0	0	0
T26	195781	289	0	0
T27	613837	0	0	0
T29	10143	0	0	0
T30	0	234	0	0
T37	19806	0	0	0
T38	35050	0	0	0
T47	0	175	0	0
T49	0	513	0	0
T51	3351	0	0	0
T80	0	295	0	0
T81	0	439	0	0
T82	0	734	0	0
T83	0	1107	0	0
T84	0	408	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634415532	10175	0	0
T21	154321	348	0	0
T22	343914	0	0	0
T23	8924	0	0	0
T25	17244	0	0	0
T26	195781	255	0	0
T27	613837	0	0	0
T29	10143	0	0	0
T30	0	246	0	0
T37	19806	0	0	0
T38	35050	0	0	0
T47	0	241	0	0
T49	0	355	0	0
T51	3351	0	0	0
T80	0	391	0	0
T81	0	350	0	0
T82	0	627	0	0
T83	0	1015	0	0
T84	0	404	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634415532	9589	0	0
T21	154321	389	0	0
T22	343914	0	0	0
T23	8924	0	0	0
T25	17244	0	0	0
T26	195781	227	0	0
T27	613837	0	0	0
T29	10143	0	0	0
T30	0	256	0	0
T37	19806	0	0	0
T38	35050	0	0	0
T47	0	143	0	0
T49	0	491	0	0
T51	3351	0	0	0
T80	0	372	0	0
T81	0	361	0	0
T82	0	567	0	0
T83	0	880	0	0
T84	0	349	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634415532	11433	0	0
T21	154321	382	0	0
T22	343914	0	0	0
T23	8924	0	0	0
T25	17244	0	0	0
T26	195781	287	0	0
T27	613837	0	0	0
T29	10143	0	0	0
T30	0	290	0	0
T37	19806	0	0	0
T38	35050	0	0	0
T47	0	259	0	0
T49	0	614	0	0
T51	3351	0	0	0
T80	0	475	0	0
T81	0	416	0	0
T82	0	643	0	0
T83	0	1015	0	0
T84	0	440	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634415532	9695	0	0
T21	154321	321	0	0
T22	343914	0	0	0
T23	8924	0	0	0
T25	17244	0	0	0
T26	195781	246	0	0
T27	613837	0	0	0
T29	10143	0	0	0
T30	0	289	0	0
T37	19806	0	0	0
T38	35050	0	0	0
T47	0	260	0	0
T49	0	512	0	0
T51	3351	0	0	0
T80	0	364	0	0
T81	0	402	0	0
T82	0	603	0	0
T83	0	909	0	0
T84	0	509	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634415532	11575	0	0
T21	154321	305	0	0
T22	343914	0	0	0
T23	8924	0	0	0
T25	17244	0	0	0
T26	195781	290	0	0
T27	613837	0	0	0
T29	10143	0	0	0
T30	0	384	0	0
T37	19806	0	0	0
T38	35050	0	0	0
T47	0	210	0	0
T49	0	607	0	0
T51	3351	0	0	0
T80	0	549	0	0
T81	0	438	0	0
T82	0	674	0	0
T83	0	978	0	0
T84	0	648	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634415532	10134	0	0
T21	154321	282	0	0
T22	343914	0	0	0
T23	8924	0	0	0
T25	17244	0	0	0
T26	195781	322	0	0
T27	613837	0	0	0
T29	10143	0	0	0
T30	0	280	0	0
T37	19806	0	0	0
T38	35050	0	0	0
T47	0	206	0	0
T49	0	482	0	0
T51	3351	0	0	0
T80	0	434	0	0
T81	0	331	0	0
T82	0	546	0	0
T83	0	992	0	0
T84	0	420	0	0