Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43986	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

330164

1

T1

11

T2

15

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	95238	1			T1	1		T2	1		T3	1
values[0x0]	131998	1			T1	8		T2	11		T3	10
values[0x1]	146914	1			T1	10		T2	10		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26533	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

347617

1

T1

15

T2

18

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1314	1			T15	29		T18	49		T28	143
valid_sources[0x01]	1545	1			T10	4		T15	19		T18	38
valid_sources[0x02]	1319	1			T10	1		T15	20		T18	46
valid_sources[0x03]	1146	1			T15	15		T18	45		T28	2
valid_sources[0x04]	1512	1			T10	2		T15	22		T18	40
valid_sources[0x05]	1539	1			T10	13		T15	15		T18	30
valid_sources[0x06]	1465	1			T10	1		T15	30		T18	43
valid_sources[0x07]	1945	1			T10	232		T15	28		T18	42
valid_sources[0x08]	1351	1			T9	1		T10	43		T15	17
valid_sources[0x09]	1363	1			T1	1		T10	1		T15	23
valid_sources[0x0a]	1407	1			T10	1		T15	16		T18	43
valid_sources[0x0b]	1285	1			T10	1		T14	1		T15	26
valid_sources[0x0c]	1627	1			T10	1		T15	17		T19	3
valid_sources[0x0d]	1448	1			T10	2		T15	28		T18	47
valid_sources[0x0e]	1241	1			T10	39		T13	2		T15	16
valid_sources[0x0f]	1150	1			T4	1		T15	16		T18	31
valid_sources[0x10]	1234	1			T10	8		T15	13		T18	43
valid_sources[0x11]	1862	1			T10	3		T15	25		T18	48
valid_sources[0x12]	1815	1			T1	3		T10	1		T15	23
valid_sources[0x13]	1247	1			T10	1		T13	1		T14	1
valid_sources[0x14]	1311	1			T3	1		T10	4		T15	27
valid_sources[0x15]	1386	1			T10	1		T15	30		T18	43
valid_sources[0x16]	1273	1			T10	2		T15	19		T17	1
valid_sources[0x17]	1214	1			T3	3		T10	110		T15	23
valid_sources[0x18]	1325	1			T4	2		T10	3		T15	28
valid_sources[0x19]	1375	1			T2	1		T15	26		T18	37
valid_sources[0x1a]	1340	1			T1	1		T10	1		T15	17
valid_sources[0x1b]	1414	1			T10	1		T15	16		T18	44
valid_sources[0x1c]	2078	1			T8	22		T10	185		T15	18
valid_sources[0x1d]	1107	1			T10	1		T15	19		T19	1
valid_sources[0x1e]	1126	1			T6	1		T15	21		T18	35
valid_sources[0x1f]	1660	1			T10	1		T27	3		T15	14
valid_sources[0x20]	1752	1			T10	2		T15	20		T18	51
valid_sources[0x21]	1964	1			T10	1		T15	22		T18	51
valid_sources[0x22]	1175	1			T15	20		T18	46		T24	8
valid_sources[0x23]	1189	1			T10	4		T15	32		T18	40
valid_sources[0x24]	1279	1			T10	7		T15	23		T18	49
valid_sources[0x25]	1308	1			T15	14		T17	1		T18	39
valid_sources[0x26]	1836	1			T10	284		T15	21		T18	39
valid_sources[0x27]	1461	1			T10	1		T15	14		T18	43
valid_sources[0x28]	1485	1			T9	2		T10	5		T15	19
valid_sources[0x29]	1639	1			T15	20		T18	48		T28	4
valid_sources[0x2a]	1217	1			T10	124		T15	17		T18	40
valid_sources[0x2b]	1404	1			T10	3		T15	21		T18	45
valid_sources[0x2c]	1449	1			T10	2		T15	16		T18	44
valid_sources[0x2d]	1631	1			T10	1		T14	1		T15	20
valid_sources[0x2e]	1738	1			T9	1		T10	148		T15	15
valid_sources[0x2f]	1244	1			T15	19		T18	40		T28	167
valid_sources[0x30]	1671	1			T10	2		T14	1		T15	13
valid_sources[0x31]	1761	1			T10	222		T15	23		T18	49
valid_sources[0x32]	1490	1			T10	1		T15	18		T18	45
valid_sources[0x33]	1297	1			T15	23		T18	52		T24	2
valid_sources[0x34]	1841	1			T15	11		T18	46		T24	6
valid_sources[0x35]	1761	1			T10	1		T15	22		T18	39
valid_sources[0x36]	1258	1			T10	9		T15	20		T18	60
valid_sources[0x37]	1444	1			T15	26		T18	46		T24	1
valid_sources[0x38]	1404	1			T15	19		T18	46		T47	2
valid_sources[0x39]	1554	1			T10	150		T15	26		T18	47
valid_sources[0x3a]	1114	1			T2	8		T15	21		T18	36
valid_sources[0x3b]	1186	1			T10	2		T15	30		T18	47
valid_sources[0x3c]	1888	1			T9	1		T14	1		T15	23
valid_sources[0x3d]	1565	1			T3	3		T10	1		T15	20
valid_sources[0x3e]	1606	1			T4	11		T10	235		T15	22
valid_sources[0x3f]	1161	1			T15	25		T18	38		T29	2
valid_sources[0x40]	1551	1			T9	1		T10	60		T27	1
valid_sources[0x41]	1637	1			T1	1		T10	1		T15	12
valid_sources[0x42]	1835	1			T9	1		T10	1		T13	1
valid_sources[0x43]	1536	1			T15	21		T18	42		T29	1
valid_sources[0x44]	1537	1			T15	16		T18	44		T24	8
valid_sources[0x45]	1306	1			T10	145		T13	2		T15	24
valid_sources[0x46]	1297	1			T2	1		T10	8		T15	18
valid_sources[0x47]	1956	1			T10	1		T15	24		T18	42
valid_sources[0x48]	1579	1			T15	21		T18	37		T39	15
valid_sources[0x49]	1592	1			T15	23		T18	43		T28	5
valid_sources[0x4a]	1324	1			T10	1		T15	17		T18	45
valid_sources[0x4b]	1197	1			T10	92		T15	25		T18	38
valid_sources[0x4c]	1717	1			T10	6		T15	21		T18	49
valid_sources[0x4d]	1557	1			T10	4		T15	20		T19	3
valid_sources[0x4e]	1226	1			T15	21		T18	41		T198	1
valid_sources[0x4f]	1742	1			T10	3		T15	22		T18	52
valid_sources[0x50]	1284	1			T15	17		T18	34		T24	3
valid_sources[0x51]	1346	1			T10	1		T15	14		T18	52
valid_sources[0x52]	1301	1			T15	20		T18	29		T45	6
valid_sources[0x53]	1559	1			T15	17		T18	34		T28	1
valid_sources[0x54]	1265	1			T1	1		T10	25		T15	13
valid_sources[0x55]	1351	1			T15	28		T18	40		T24	5
valid_sources[0x56]	1318	1			T10	1		T15	18		T18	49
valid_sources[0x57]	1501	1			T4	1		T9	1		T15	19
valid_sources[0x58]	1052	1			T10	4		T15	21		T18	36
valid_sources[0x59]	1768	1			T9	3		T10	124		T15	20
valid_sources[0x5a]	1422	1			T4	2		T10	2		T15	21
valid_sources[0x5b]	1237	1			T10	1		T15	15		T18	46
valid_sources[0x5c]	1107	1			T10	8		T15	20		T18	40
valid_sources[0x5d]	1709	1			T10	134		T15	24		T18	46
valid_sources[0x5e]	1199	1			T15	19		T18	39		T24	3
valid_sources[0x5f]	1462	1			T15	22		T18	55		T198	1
valid_sources[0x60]	2068	1			T15	18		T18	36		T44	9
valid_sources[0x61]	1521	1			T10	146		T15	23		T18	30
valid_sources[0x62]	1088	1			T10	1		T15	21		T18	35
valid_sources[0x63]	1476	1			T10	1		T15	20		T18	51
valid_sources[0x64]	1451	1			T1	1		T10	1		T15	21
valid_sources[0x65]	1379	1			T15	34		T18	51		T24	10
valid_sources[0x66]	1254	1			T15	29		T18	46		T39	14
valid_sources[0x67]	1835	1			T10	2		T15	23		T18	53
valid_sources[0x68]	1365	1			T15	14		T18	43		T28	25
valid_sources[0x69]	1450	1			T14	1		T15	20		T18	49
valid_sources[0x6a]	1762	1			T15	19		T18	49		T24	100
valid_sources[0x6b]	1212	1			T10	1		T15	26		T18	31
valid_sources[0x6c]	1206	1			T2	4		T15	22		T18	39
valid_sources[0x6d]	1392	1			T6	1		T15	20		T18	49
valid_sources[0x6e]	1295	1			T10	33		T15	20		T19	4
valid_sources[0x6f]	1739	1			T13	5		T15	22		T18	35
valid_sources[0x70]	1045	1			T10	8		T15	29		T18	53
valid_sources[0x71]	1695	1			T10	4		T14	1		T15	23
valid_sources[0x72]	1290	1			T3	2		T10	10		T15	16
valid_sources[0x73]	1723	1			T1	1		T10	1		T15	22
valid_sources[0x74]	1646	1			T9	1		T15	26		T19	1
valid_sources[0x75]	2327	1			T10	15		T15	25		T18	57
valid_sources[0x76]	1674	1			T10	81		T27	2		T15	25
valid_sources[0x77]	1393	1			T2	4		T15	21		T18	38
valid_sources[0x78]	1575	1			T6	2		T10	154		T15	28
valid_sources[0x79]	1364	1			T10	2		T14	1		T15	29
valid_sources[0x7a]	1433	1			T15	21		T18	37		T28	1
valid_sources[0x7b]	1399	1			T10	23		T15	20		T18	36
valid_sources[0x7c]	1507	1			T10	1		T15	21		T18	59
valid_sources[0x7d]	1517	1			T10	2		T15	20		T17	2
valid_sources[0x7e]	1686	1			T15	30		T18	36		T24	70
valid_sources[0x7f]	1267	1			T10	1		T15	12		T18	50
valid_sources[0x80]	1257	1			T15	29		T18	29		T39	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

82119

1

T4

1

T5

1

T6

1

values[0x0]

all_enables

biggest_size

124418

1

T1

6

T2

9

T3

6

values[0x1]

all_enables

biggest_size

123627

1

T1

5

T2

6

T3

5