Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	588897138	338497	0	0
wdog_bark_thold_rd_A	588897138	8130	0	0
wdog_bite_thold_rd_A	588897138	7496	0	0
wdog_ctrl_rd_A	588897138	7294	0	0
wdog_regwen_rd_A	588897138	8418	0	0
wkup_ctrl_rd_A	588897138	7529	0	0
wkup_thold_hi_rd_A	588897138	8113	0	0
wkup_thold_lo_rd_A	588897138	7434	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588897138	338497	0	0
T10	227568	5719	0	0
T13	12605	0	0	0
T14	981792	0	0	0
T15	206038	5736	0	0
T16	8567	0	0	0
T17	432788	0	0	0
T18	0	11562	0	0
T24	0	3813	0	0
T25	384851	0	0	0
T26	102550	0	0	0
T27	12813	0	0	0
T28	0	6345	0	0
T33	56565	0	0	0
T39	0	4478	0	0
T40	0	15334	0	0
T41	0	8901	0	0
T42	0	7529	0	0
T43	0	3889	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588897138	8130	0	0
T10	227568	596	0	0
T13	12605	0	0	0
T14	981792	0	0	0
T15	206038	0	0	0
T16	8567	0	0	0
T17	432788	0	0	0
T25	384851	0	0	0
T26	102550	0	0	0
T27	12813	0	0	0
T33	56565	0	0	0
T39	0	366	0	0
T41	0	702	0	0
T43	0	451	0	0
T70	0	467	0	0
T71	0	788	0	0
T72	0	541	0	0
T73	0	1010	0	0
T74	0	398	0	0
T75	0	354	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588897138	7496	0	0
T10	227568	569	0	0
T13	12605	0	0	0
T14	981792	0	0	0
T15	206038	0	0	0
T16	8567	0	0	0
T17	432788	0	0	0
T25	384851	0	0	0
T26	102550	0	0	0
T27	12813	0	0	0
T33	56565	0	0	0
T39	0	315	0	0
T41	0	793	0	0
T43	0	318	0	0
T70	0	408	0	0
T71	0	673	0	0
T72	0	460	0	0
T73	0	1084	0	0
T74	0	353	0	0
T75	0	269	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588897138	7294	0	0
T10	227568	555	0	0
T13	12605	0	0	0
T14	981792	0	0	0
T15	206038	0	0	0
T16	8567	0	0	0
T17	432788	0	0	0
T25	384851	0	0	0
T26	102550	0	0	0
T27	12813	0	0	0
T33	56565	0	0	0
T39	0	348	0	0
T41	0	793	0	0
T43	0	320	0	0
T70	0	463	0	0
T71	0	643	0	0
T72	0	459	0	0
T73	0	893	0	0
T74	0	304	0	0
T75	0	314	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588897138	8418	0	0
T10	227568	510	0	0
T13	12605	0	0	0
T14	981792	0	0	0
T15	206038	0	0	0
T16	8567	0	0	0
T17	432788	0	0	0
T25	384851	0	0	0
T26	102550	0	0	0
T27	12813	0	0	0
T33	56565	0	0	0
T39	0	445	0	0
T41	0	958	0	0
T43	0	328	0	0
T70	0	409	0	0
T71	0	822	0	0
T72	0	519	0	0
T73	0	1107	0	0
T74	0	371	0	0
T75	0	400	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588897138	7529	0	0
T10	227568	424	0	0
T13	12605	0	0	0
T14	981792	0	0	0
T15	206038	0	0	0
T16	8567	0	0	0
T17	432788	0	0	0
T25	384851	0	0	0
T26	102550	0	0	0
T27	12813	0	0	0
T33	56565	0	0	0
T39	0	418	0	0
T41	0	852	0	0
T43	0	351	0	0
T70	0	440	0	0
T71	0	751	0	0
T72	0	431	0	0
T73	0	954	0	0
T74	0	402	0	0
T75	0	345	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588897138	8113	0	0
T10	227568	542	0	0
T13	12605	0	0	0
T14	981792	0	0	0
T15	206038	0	0	0
T16	8567	0	0	0
T17	432788	0	0	0
T25	384851	0	0	0
T26	102550	0	0	0
T27	12813	0	0	0
T33	56565	0	0	0
T39	0	464	0	0
T41	0	959	0	0
T43	0	385	0	0
T70	0	539	0	0
T71	0	704	0	0
T72	0	446	0	0
T73	0	1061	0	0
T74	0	493	0	0
T75	0	375	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588897138	7434	0	0
T10	227568	481	0	0
T13	12605	0	0	0
T14	981792	0	0	0
T15	206038	0	0	0
T16	8567	0	0	0
T17	432788	0	0	0
T25	384851	0	0	0
T26	102550	0	0	0
T27	12813	0	0	0
T33	56565	0	0	0
T39	0	365	0	0
T41	0	901	0	0
T43	0	298	0	0
T70	0	420	0	0
T71	0	689	0	0
T72	0	498	0	0
T73	0	870	0	0
T74	0	372	0	0
T75	0	363	0	0