Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43356	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

322170

1

T1

11

T2

16

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	93141	1			T1	1		T2	1		T3	1
values[0x0]	128919	1			T1	9		T2	12		T3	5
values[0x1]	143466	1			T1	8		T2	9		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26521	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

339005

1

T1

11

T2

16

T3

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1653	1			T7	2		T12	15		T17	18
valid_sources[0x01]	1650	1			T12	25		T33	2		T17	31
valid_sources[0x02]	1783	1			T12	15		T17	24		T20	5
valid_sources[0x03]	1143	1			T12	11		T17	22		T20	14
valid_sources[0x04]	1581	1			T12	29		T17	19		T20	18
valid_sources[0x05]	1483	1			T12	21		T17	21		T20	9
valid_sources[0x06]	1312	1			T12	17		T17	18		T20	10
valid_sources[0x07]	1173	1			T12	11		T14	7		T17	24
valid_sources[0x08]	1081	1			T12	27		T16	4		T17	31
valid_sources[0x09]	1312	1			T12	16		T17	36		T20	23
valid_sources[0x0a]	1856	1			T12	25		T13	1		T17	18
valid_sources[0x0b]	1326	1			T8	1		T10	2		T12	12
valid_sources[0x0c]	1456	1			T12	23		T13	1		T17	14
valid_sources[0x0d]	2087	1			T12	23		T17	20		T20	10
valid_sources[0x0e]	1291	1			T12	19		T17	24		T20	14
valid_sources[0x0f]	1482	1			T12	12		T13	1		T17	22
valid_sources[0x10]	1323	1			T12	23		T17	29		T20	19
valid_sources[0x11]	1210	1			T9	1		T12	20		T17	35
valid_sources[0x12]	1477	1			T12	12		T17	37		T20	8
valid_sources[0x13]	1144	1			T10	1		T12	14		T17	29
valid_sources[0x14]	1294	1			T12	17		T13	1		T17	28
valid_sources[0x15]	1402	1			T12	17		T17	20		T20	11
valid_sources[0x16]	1552	1			T12	11		T17	20		T20	20
valid_sources[0x17]	2128	1			T12	27		T17	29		T20	9
valid_sources[0x18]	1546	1			T7	4		T12	27		T17	24
valid_sources[0x19]	958	1			T10	1		T12	19		T22	2
valid_sources[0x1a]	1493	1			T12	15		T17	27		T31	1
valid_sources[0x1b]	1299	1			T12	16		T17	34		T31	2
valid_sources[0x1c]	1103	1			T12	20		T17	22		T20	14
valid_sources[0x1d]	1512	1			T12	17		T13	1		T17	25
valid_sources[0x1e]	1104	1			T12	15		T13	1		T17	17
valid_sources[0x1f]	1642	1			T12	17		T17	27		T31	1
valid_sources[0x20]	989	1			T12	21		T17	13		T20	7
valid_sources[0x21]	1269	1			T12	26		T17	13		T20	13
valid_sources[0x22]	1292	1			T9	1		T12	16		T17	20
valid_sources[0x23]	981	1			T9	1		T12	18		T17	29
valid_sources[0x24]	1782	1			T2	22		T5	2		T12	19
valid_sources[0x25]	1212	1			T12	19		T17	17		T20	11
valid_sources[0x26]	1252	1			T12	17		T17	21		T20	13
valid_sources[0x27]	1224	1			T12	15		T17	27		T20	12
valid_sources[0x28]	1665	1			T12	17		T17	19		T20	12
valid_sources[0x29]	1952	1			T12	15		T33	1		T17	27
valid_sources[0x2a]	1481	1			T12	27		T22	1		T17	22
valid_sources[0x2b]	1502	1			T5	11		T12	27		T17	16
valid_sources[0x2c]	1704	1			T1	18		T12	21		T17	27
valid_sources[0x2d]	1166	1			T12	21		T17	19		T20	10
valid_sources[0x2e]	1425	1			T12	12		T17	15		T20	15
valid_sources[0x2f]	1040	1			T10	1		T12	19		T17	17
valid_sources[0x30]	1460	1			T12	18		T17	29		T20	16
valid_sources[0x31]	1180	1			T12	24		T33	1		T17	24
valid_sources[0x32]	1488	1			T12	17		T33	1		T17	29
valid_sources[0x33]	1638	1			T7	1		T12	18		T17	14
valid_sources[0x34]	1763	1			T12	14		T17	16		T20	8
valid_sources[0x35]	1467	1			T12	12		T17	10		T20	12
valid_sources[0x36]	1227	1			T9	2		T12	17		T17	17
valid_sources[0x37]	1175	1			T12	27		T22	5		T17	18
valid_sources[0x38]	1956	1			T12	21		T17	28		T20	8
valid_sources[0x39]	1989	1			T12	18		T17	41		T20	8
valid_sources[0x3a]	880	1			T12	20		T17	38		T20	5
valid_sources[0x3b]	1477	1			T9	2		T12	11		T17	17
valid_sources[0x3c]	1667	1			T12	13		T13	1		T17	17
valid_sources[0x3d]	1284	1			T12	19		T17	12		T20	9
valid_sources[0x3e]	1552	1			T12	22		T17	24		T20	10
valid_sources[0x3f]	1127	1			T10	1		T12	18		T22	1
valid_sources[0x40]	1717	1			T12	22		T17	15		T20	16
valid_sources[0x41]	1621	1			T12	23		T17	25		T20	19
valid_sources[0x42]	1118	1			T10	1		T12	10		T17	27
valid_sources[0x43]	974	1			T12	20		T17	20		T20	12
valid_sources[0x44]	1056	1			T9	1		T12	21		T17	21
valid_sources[0x45]	1334	1			T12	18		T17	22		T20	12
valid_sources[0x46]	1118	1			T9	3		T12	18		T17	16
valid_sources[0x47]	1161	1			T12	19		T17	19		T20	14
valid_sources[0x48]	1565	1			T12	16		T17	15		T31	1
valid_sources[0x49]	1604	1			T12	23		T17	24		T20	8
valid_sources[0x4a]	1686	1			T8	10		T12	17		T13	1
valid_sources[0x4b]	1393	1			T12	15		T14	6		T33	1
valid_sources[0x4c]	1772	1			T10	1		T12	25		T17	13
valid_sources[0x4d]	1175	1			T12	13		T17	24		T20	12
valid_sources[0x4e]	1297	1			T12	23		T17	19		T20	11
valid_sources[0x4f]	1308	1			T10	1		T12	21		T17	32
valid_sources[0x50]	1248	1			T12	18		T33	2		T17	13
valid_sources[0x51]	1095	1			T8	1		T12	20		T17	21
valid_sources[0x52]	2010	1			T12	27		T17	22		T31	1
valid_sources[0x53]	1306	1			T12	23		T17	28		T20	13
valid_sources[0x54]	1833	1			T12	19		T17	16		T20	11
valid_sources[0x55]	1121	1			T8	5		T9	1		T12	17
valid_sources[0x56]	1433	1			T12	22		T17	14		T20	10
valid_sources[0x57]	1356	1			T12	15		T17	20		T20	7
valid_sources[0x58]	1192	1			T12	15		T17	14		T20	14
valid_sources[0x59]	1629	1			T6	21		T12	23		T17	20
valid_sources[0x5a]	1894	1			T7	1		T12	17		T17	23
valid_sources[0x5b]	1649	1			T12	21		T13	1		T17	28
valid_sources[0x5c]	1293	1			T3	18		T12	18		T22	3
valid_sources[0x5d]	1285	1			T12	21		T17	21		T20	17
valid_sources[0x5e]	1329	1			T12	25		T22	3		T17	39
valid_sources[0x5f]	1091	1			T12	22		T17	25		T18	22
valid_sources[0x60]	2248	1			T12	19		T17	17		T20	13
valid_sources[0x61]	1343	1			T12	22		T17	23		T20	7
valid_sources[0x62]	1620	1			T12	23		T17	19		T20	9
valid_sources[0x63]	1957	1			T12	16		T17	15		T20	9
valid_sources[0x64]	1402	1			T12	18		T17	19		T20	18
valid_sources[0x65]	1573	1			T12	18		T17	14		T20	14
valid_sources[0x66]	1594	1			T12	12		T17	27		T31	3
valid_sources[0x67]	1444	1			T7	1		T12	17		T17	12
valid_sources[0x68]	1925	1			T12	18		T17	18		T20	8
valid_sources[0x69]	1256	1			T12	16		T17	34		T20	10
valid_sources[0x6a]	1494	1			T12	12		T17	27		T20	14
valid_sources[0x6b]	1387	1			T7	1		T12	26		T17	24
valid_sources[0x6c]	1305	1			T12	19		T17	26		T20	9
valid_sources[0x6d]	1379	1			T12	21		T17	14		T20	15
valid_sources[0x6e]	1276	1			T12	25		T13	1		T17	16
valid_sources[0x6f]	1510	1			T12	25		T17	34		T20	19
valid_sources[0x70]	2042	1			T12	23		T17	23		T20	15
valid_sources[0x71]	1587	1			T12	16		T17	16		T20	18
valid_sources[0x72]	1600	1			T7	2		T12	20		T17	37
valid_sources[0x73]	1207	1			T12	22		T17	29		T20	16
valid_sources[0x74]	1435	1			T12	16		T17	19		T20	8
valid_sources[0x75]	944	1			T12	21		T17	22		T20	10
valid_sources[0x76]	1403	1			T5	5		T12	21		T17	16
valid_sources[0x77]	1808	1			T12	15		T17	25		T20	13
valid_sources[0x78]	1503	1			T10	1		T12	17		T17	27
valid_sources[0x79]	1331	1			T6	1		T12	23		T17	15
valid_sources[0x7a]	1500	1			T12	9		T17	30		T20	17
valid_sources[0x7b]	1926	1			T12	18		T17	20		T19	1
valid_sources[0x7c]	1350	1			T12	13		T17	35		T19	1
valid_sources[0x7d]	1240	1			T12	23		T17	31		T20	13
valid_sources[0x7e]	1616	1			T9	1		T10	1		T12	20
valid_sources[0x7f]	1441	1			T12	21		T17	36		T20	5
valid_sources[0x80]	1622	1			T12	14		T17	31		T20	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

80067

1

T1

1

T2

1

T9

1

values[0x0]

all_enables

biggest_size

121292

1

T1

7

T2

9

T3

1

values[0x1]

all_enables

biggest_size

120811

1

T1

3

T2

6

T3

10