Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	651951300	321538	0	0
wdog_bark_thold_rd_A	651951300	8915	0	0
wdog_bite_thold_rd_A	651951300	7624	0	0
wdog_ctrl_rd_A	651951300	7807	0	0
wdog_regwen_rd_A	651951300	8517	0	0
wkup_ctrl_rd_A	651951300	7613	0	0
wkup_thold_hi_rd_A	651951300	8796	0	0
wkup_thold_lo_rd_A	651951300	7653	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651951300	321538	0	0
T12	206629	3852	0	0
T13	731614	0	0	0
T14	13026	0	0	0
T15	28995	0	0	0
T16	223285	0	0	0
T17	342674	4992	0	0
T18	17677	0	0	0
T20	0	2567	0	0
T22	34474	0	0	0
T29	412429	0	0	0
T33	21949	0	0	0
T35	0	10610	0	0
T39	0	3107	0	0
T44	0	7728	0	0
T45	0	7654	0	0
T46	0	4141	0	0
T47	0	578	0	0
T48	0	6444	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651951300	8915	0	0
T17	342674	618	0	0
T18	17677	0	0	0
T19	190906	0	0	0
T20	190741	0	0	0
T21	129812	0	0	0
T30	656629	0	0	0
T31	34033	0	0	0
T32	20549	0	0	0
T34	9018	0	0	0
T39	0	392	0	0
T44	0	793	0	0
T46	0	383	0	0
T47	0	110	0	0
T71	0	727	0	0
T72	0	512	0	0
T73	0	613	0	0
T74	0	182	0	0
T75	0	497	0	0
T76	37530	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651951300	7624	0	0
T17	342674	541	0	0
T18	17677	0	0	0
T19	190906	0	0	0
T20	190741	0	0	0
T21	129812	0	0	0
T30	656629	0	0	0
T31	34033	0	0	0
T32	20549	0	0	0
T34	9018	0	0	0
T39	0	358	0	0
T44	0	688	0	0
T46	0	479	0	0
T47	0	80	0	0
T71	0	767	0	0
T72	0	360	0	0
T73	0	523	0	0
T74	0	160	0	0
T75	0	397	0	0
T76	37530	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651951300	7807	0	0
T17	342674	470	0	0
T18	17677	0	0	0
T19	190906	0	0	0
T20	190741	0	0	0
T21	129812	0	0	0
T30	656629	0	0	0
T31	34033	0	0	0
T32	20549	0	0	0
T34	9018	0	0	0
T39	0	293	0	0
T44	0	758	0	0
T46	0	480	0	0
T47	0	88	0	0
T71	0	656	0	0
T72	0	340	0	0
T73	0	488	0	0
T74	0	133	0	0
T75	0	484	0	0
T76	37530	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651951300	8517	0	0
T17	342674	480	0	0
T18	17677	0	0	0
T19	190906	0	0	0
T20	190741	0	0	0
T21	129812	0	0	0
T30	656629	0	0	0
T31	34033	0	0	0
T32	20549	0	0	0
T34	9018	0	0	0
T39	0	513	0	0
T44	0	845	0	0
T46	0	496	0	0
T47	0	124	0	0
T71	0	732	0	0
T72	0	355	0	0
T73	0	628	0	0
T74	0	110	0	0
T75	0	477	0	0
T76	37530	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651951300	7613	0	0
T17	342674	423	0	0
T18	17677	0	0	0
T19	190906	0	0	0
T20	190741	0	0	0
T21	129812	0	0	0
T30	656629	0	0	0
T31	34033	0	0	0
T32	20549	0	0	0
T34	9018	0	0	0
T39	0	367	0	0
T44	0	831	0	0
T46	0	419	0	0
T47	0	59	0	0
T71	0	722	0	0
T72	0	328	0	0
T73	0	513	0	0
T74	0	97	0	0
T75	0	485	0	0
T76	37530	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651951300	8796	0	0
T17	342674	562	0	0
T18	17677	0	0	0
T19	190906	0	0	0
T20	190741	0	0	0
T21	129812	0	0	0
T30	656629	0	0	0
T31	34033	0	0	0
T32	20549	0	0	0
T34	9018	0	0	0
T39	0	406	0	0
T44	0	884	0	0
T46	0	462	0	0
T47	0	58	0	0
T71	0	670	0	0
T72	0	456	0	0
T73	0	562	0	0
T74	0	167	0	0
T75	0	607	0	0
T76	37530	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651951300	7653	0	0
T17	342674	473	0	0
T18	17677	0	0	0
T19	190906	0	0	0
T20	190741	0	0	0
T21	129812	0	0	0
T30	656629	0	0	0
T31	34033	0	0	0
T32	20549	0	0	0
T34	9018	0	0	0
T39	0	343	0	0
T44	0	614	0	0
T46	0	539	0	0
T47	0	66	0	0
T71	0	552	0	0
T72	0	397	0	0
T73	0	601	0	0
T74	0	156	0	0
T75	0	479	0	0
T76	37530	0	0	0