Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
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Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 41610 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 313184 1 T1 16 T2 12 T3 15



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 90483 1 T1 1 T2 1 T3 1
values[0x0] 125513 1 T1 11 T2 9 T3 11
values[0x1] 138798 1 T1 10 T2 8 T3 6



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 25441 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 329353 1 T1 17 T2 12 T3 16



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1883 1 T18 15 T22 12 T35 38
valid_sources[0x01] 1163 1 T4 1 T18 20 T22 1
valid_sources[0x02] 1113 1 T18 9 T22 5 T35 23
valid_sources[0x03] 2282 1 T18 6 T19 426 T22 3
valid_sources[0x04] 1542 1 T18 16 T22 20 T35 31
valid_sources[0x05] 1689 1 T18 11 T22 15 T31 1
valid_sources[0x06] 1173 1 T18 6 T19 182 T22 7
valid_sources[0x07] 1517 1 T18 12 T19 131 T52 1
valid_sources[0x08] 947 1 T18 7 T22 1 T35 24
valid_sources[0x09] 1914 1 T18 9 T54 2 T22 2
valid_sources[0x0a] 1609 1 T18 13 T30 1 T22 8
valid_sources[0x0b] 1402 1 T18 17 T33 5 T22 4
valid_sources[0x0c] 1375 1 T29 6 T34 4 T18 5
valid_sources[0x0d] 1165 1 T18 7 T52 1 T22 4
valid_sources[0x0e] 1358 1 T18 11 T22 10 T35 17
valid_sources[0x0f] 1192 1 T34 3 T18 6 T22 3
valid_sources[0x10] 1437 1 T16 1 T18 11 T22 12
valid_sources[0x11] 1291 1 T18 5 T22 6 T35 18
valid_sources[0x12] 1212 1 T18 7 T22 3 T31 1
valid_sources[0x13] 1400 1 T18 4 T201 1 T22 2
valid_sources[0x14] 1252 1 T18 17 T22 5 T35 19
valid_sources[0x15] 1486 1 T18 7 T22 14 T82 19
valid_sources[0x16] 1353 1 T18 11 T22 3 T35 37
valid_sources[0x17] 1164 1 T18 6 T19 17 T22 1
valid_sources[0x18] 1768 1 T18 6 T30 2 T22 6
valid_sources[0x19] 1346 1 T18 7 T22 9 T31 1
valid_sources[0x1a] 1253 1 T29 2 T18 15 T81 2
valid_sources[0x1b] 1957 1 T18 8 T81 2 T201 4
valid_sources[0x1c] 1462 1 T29 1 T18 8 T53 1
valid_sources[0x1d] 2047 1 T18 12 T52 1 T22 10
valid_sources[0x1e] 1146 1 T18 9 T30 1 T22 6
valid_sources[0x1f] 1250 1 T4 1 T18 9 T30 1
valid_sources[0x20] 1513 1 T16 1 T18 13 T22 9
valid_sources[0x21] 1176 1 T18 4 T52 1 T53 1
valid_sources[0x22] 1275 1 T4 1 T18 9 T22 5
valid_sources[0x23] 1636 1 T8 5 T18 9 T19 13
valid_sources[0x24] 1023 1 T18 8 T22 5 T35 54
valid_sources[0x25] 1321 1 T18 11 T22 3 T35 65
valid_sources[0x26] 1039 1 T18 5 T22 9 T35 28
valid_sources[0x27] 1381 1 T18 5 T54 1 T22 6
valid_sources[0x28] 1614 1 T18 6 T22 7 T35 55
valid_sources[0x29] 1460 1 T12 1 T30 2 T22 6
valid_sources[0x2a] 1593 1 T8 2 T26 19 T18 8
valid_sources[0x2b] 1537 1 T18 5 T19 180 T22 4
valid_sources[0x2c] 1444 1 T18 7 T22 6 T35 32
valid_sources[0x2d] 1973 1 T29 1 T18 14 T22 8
valid_sources[0x2e] 1127 1 T15 22 T18 12 T22 6
valid_sources[0x2f] 982 1 T18 4 T19 1 T22 9
valid_sources[0x30] 1310 1 T5 1 T18 10 T22 17
valid_sources[0x31] 1205 1 T5 2 T18 7 T22 12
valid_sources[0x32] 1114 1 T29 2 T18 19 T22 16
valid_sources[0x33] 1564 1 T5 1 T18 18 T19 6
valid_sources[0x34] 1790 1 T10 1 T18 12 T19 188
valid_sources[0x35] 2068 1 T18 10 T52 1 T22 6
valid_sources[0x36] 986 1 T18 14 T22 13 T35 24
valid_sources[0x37] 1064 1 T18 12 T19 3 T22 2
valid_sources[0x38] 1118 1 T18 3 T22 5 T35 22
valid_sources[0x39] 930 1 T18 8 T22 4 T35 30
valid_sources[0x3a] 1408 1 T18 22 T54 1 T22 11
valid_sources[0x3b] 1416 1 T4 4 T9 5 T18 8
valid_sources[0x3c] 1469 1 T18 17 T19 1 T22 10
valid_sources[0x3d] 1406 1 T18 13 T22 11 T35 15
valid_sources[0x3e] 1213 1 T18 6 T54 1 T22 6
valid_sources[0x3f] 1653 1 T4 1 T18 19 T19 145
valid_sources[0x40] 1242 1 T18 11 T22 10 T35 29
valid_sources[0x41] 1169 1 T18 8 T22 1 T32 2
valid_sources[0x42] 1526 1 T18 9 T22 8 T216 1
valid_sources[0x43] 1438 1 T12 5 T18 7 T54 1
valid_sources[0x44] 1094 1 T18 12 T22 8 T35 35
valid_sources[0x45] 1289 1 T18 11 T52 1 T22 3
valid_sources[0x46] 1091 1 T18 15 T22 7 T35 14
valid_sources[0x47] 1243 1 T10 1 T29 2 T18 8
valid_sources[0x48] 1197 1 T18 15 T52 1 T54 1
valid_sources[0x49] 1661 1 T18 13 T22 4 T35 15
valid_sources[0x4a] 1814 1 T34 2 T18 14 T22 4
valid_sources[0x4b] 1432 1 T18 13 T22 1 T35 38
valid_sources[0x4c] 1342 1 T18 8 T22 3 T35 35
valid_sources[0x4d] 1415 1 T18 12 T22 9 T35 41
valid_sources[0x4e] 1588 1 T10 1 T18 11 T22 2
valid_sources[0x4f] 1215 1 T18 10 T22 2 T31 1
valid_sources[0x50] 1501 1 T18 12 T19 65 T22 1
valid_sources[0x51] 1377 1 T18 5 T54 1 T22 6
valid_sources[0x52] 1745 1 T18 17 T22 4 T35 11
valid_sources[0x53] 1314 1 T16 1 T18 9 T22 12
valid_sources[0x54] 1580 1 T18 12 T19 1 T81 2
valid_sources[0x55] 1247 1 T16 2 T18 10 T22 6
valid_sources[0x56] 1348 1 T18 14 T22 15 T35 15
valid_sources[0x57] 1235 1 T12 1 T18 9 T22 14
valid_sources[0x58] 990 1 T10 1 T18 6 T54 2
valid_sources[0x59] 1330 1 T13 19 T18 17 T201 2
valid_sources[0x5a] 1420 1 T18 17 T22 12 T35 33
valid_sources[0x5b] 1344 1 T29 1 T18 4 T22 15
valid_sources[0x5c] 1316 1 T5 1 T18 7 T22 3
valid_sources[0x5d] 1455 1 T12 1 T18 7 T30 2
valid_sources[0x5e] 1409 1 T18 15 T81 1 T22 14
valid_sources[0x5f] 1471 1 T10 2 T18 14 T22 8
valid_sources[0x60] 1570 1 T10 1 T18 19 T19 20
valid_sources[0x61] 1401 1 T18 20 T19 61 T52 1
valid_sources[0x62] 986 1 T12 1 T18 8 T22 10
valid_sources[0x63] 1284 1 T18 17 T22 4 T35 19
valid_sources[0x64] 999 1 T18 16 T22 1 T35 18
valid_sources[0x65] 1378 1 T18 7 T22 15 T35 22
valid_sources[0x66] 1624 1 T10 1 T18 4 T22 15
valid_sources[0x67] 1736 1 T4 1 T18 16 T22 5
valid_sources[0x68] 1583 1 T4 1 T7 22 T18 10
valid_sources[0x69] 1177 1 T18 7 T22 4 T35 33
valid_sources[0x6a] 1327 1 T18 13 T22 19 T35 31
valid_sources[0x6b] 1083 1 T18 12 T19 6 T54 1
valid_sources[0x6c] 1347 1 T18 11 T22 8 T35 36
valid_sources[0x6d] 1968 1 T5 1 T18 7 T201 1
valid_sources[0x6e] 1086 1 T18 13 T22 14 T35 41
valid_sources[0x6f] 1440 1 T18 7 T19 71 T52 1
valid_sources[0x70] 1150 1 T8 3 T18 9 T22 5
valid_sources[0x71] 1282 1 T18 14 T22 4 T35 29
valid_sources[0x72] 2195 1 T9 2 T29 1 T18 8
valid_sources[0x73] 2041 1 T18 6 T22 18 T35 27
valid_sources[0x74] 1564 1 T34 11 T18 8 T81 1
valid_sources[0x75] 1110 1 T18 14 T19 129 T54 1
valid_sources[0x76] 1171 1 T12 6 T18 8 T53 6
valid_sources[0x77] 1276 1 T18 4 T19 22 T22 11
valid_sources[0x78] 1025 1 T16 1 T18 4 T22 13
valid_sources[0x79] 1325 1 T18 25 T22 6 T35 21
valid_sources[0x7a] 1498 1 T22 5 T35 30 T46 9
valid_sources[0x7b] 1265 1 T18 11 T30 3 T81 1
valid_sources[0x7c] 1219 1 T18 6 T52 1 T22 17
valid_sources[0x7d] 1185 1 T16 5 T17 8 T18 10
valid_sources[0x7e] 1358 1 T18 10 T22 5 T35 29
valid_sources[0x7f] 1222 1 T18 4 T22 6 T35 21
valid_sources[0x80] 988 1 T18 7 T52 1 T22 6



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 77629 1 T2 1 T9 1 T12 1
values[0x0] all_enables biggest_size 118226 1 T1 9 T2 5 T3 10
values[0x1] all_enables biggest_size 117329 1 T1 7 T2 6 T3 5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%