Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	560099105	321281	0	0
wdog_bark_thold_rd_A	560099105	4808	0	0
wdog_bite_thold_rd_A	560099105	4711	0	0
wdog_ctrl_rd_A	560099105	4644	0	0
wdog_regwen_rd_A	560099105	5740	0	0
wkup_ctrl_rd_A	560099105	4582	0	0
wkup_thold_hi_rd_A	560099105	4516	0	0
wkup_thold_lo_rd_A	560099105	4421	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560099105	321281	0	0
T18	149716	2198	0	0
T19	296909	4207	0	0
T20	13468	0	0	0
T22	0	1833	0	0
T23	819461	0	0	0
T30	42019	0	0	0
T33	36602	0	0	0
T35	0	7300	0	0
T39	792801	0	0	0
T46	0	3095	0	0
T47	0	3140	0	0
T48	0	10263	0	0
T49	0	3947	0	0
T50	0	11663	0	0
T51	0	3377	0	0
T52	406741	0	0	0
T53	5130	0	0	0
T54	52482	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560099105	4808	0	0
T36	0	10	0	0
T51	140351	302	0	0
T83	0	131	0	0
T84	0	365	0	0
T85	0	664	0	0
T86	0	430	0	0
T87	0	93	0	0
T88	0	514	0	0
T89	0	395	0	0
T90	0	506	0	0
T91	166010	0	0	0
T92	18803	0	0	0
T93	189706	0	0	0
T94	703922	0	0	0
T95	24698	0	0	0
T96	261261	0	0	0
T97	7789	0	0	0
T98	11923	0	0	0
T99	820664	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560099105	4711	0	0
T36	0	10	0	0
T51	140351	285	0	0
T83	0	204	0	0
T84	0	416	0	0
T85	0	624	0	0
T86	0	421	0	0
T87	0	100	0	0
T88	0	529	0	0
T89	0	470	0	0
T90	0	389	0	0
T91	166010	0	0	0
T92	18803	0	0	0
T93	189706	0	0	0
T94	703922	0	0	0
T95	24698	0	0	0
T96	261261	0	0	0
T97	7789	0	0	0
T98	11923	0	0	0
T99	820664	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560099105	4644	0	0
T36	0	4	0	0
T51	140351	367	0	0
T83	0	175	0	0
T84	0	324	0	0
T85	0	650	0	0
T86	0	306	0	0
T87	0	84	0	0
T88	0	491	0	0
T89	0	317	0	0
T90	0	557	0	0
T91	166010	0	0	0
T92	18803	0	0	0
T93	189706	0	0	0
T94	703922	0	0	0
T95	24698	0	0	0
T96	261261	0	0	0
T97	7789	0	0	0
T98	11923	0	0	0
T99	820664	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560099105	5740	0	0
T36	0	6	0	0
T51	140351	382	0	0
T83	0	205	0	0
T84	0	384	0	0
T85	0	598	0	0
T86	0	401	0	0
T87	0	170	0	0
T88	0	559	0	0
T89	0	391	0	0
T90	0	551	0	0
T91	166010	0	0	0
T92	18803	0	0	0
T93	189706	0	0	0
T94	703922	0	0	0
T95	24698	0	0	0
T96	261261	0	0	0
T97	7789	0	0	0
T98	11923	0	0	0
T99	820664	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560099105	4582	0	0
T36	0	10	0	0
T51	140351	335	0	0
T83	0	118	0	0
T84	0	377	0	0
T85	0	577	0	0
T86	0	410	0	0
T87	0	105	0	0
T88	0	507	0	0
T89	0	349	0	0
T90	0	442	0	0
T91	166010	0	0	0
T92	18803	0	0	0
T93	189706	0	0	0
T94	703922	0	0	0
T95	24698	0	0	0
T96	261261	0	0	0
T97	7789	0	0	0
T98	11923	0	0	0
T99	820664	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560099105	4516	0	0
T36	0	11	0	0
T51	140351	352	0	0
T83	0	162	0	0
T84	0	322	0	0
T85	0	604	0	0
T86	0	370	0	0
T87	0	88	0	0
T88	0	512	0	0
T89	0	345	0	0
T90	0	468	0	0
T91	166010	0	0	0
T92	18803	0	0	0
T93	189706	0	0	0
T94	703922	0	0	0
T95	24698	0	0	0
T96	261261	0	0	0
T97	7789	0	0	0
T98	11923	0	0	0
T99	820664	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560099105	4421	0	0
T36	0	5	0	0
T51	140351	292	0	0
T83	0	112	0	0
T84	0	357	0	0
T85	0	592	0	0
T86	0	342	0	0
T87	0	148	0	0
T88	0	471	0	0
T89	0	351	0	0
T90	0	455	0	0
T91	166010	0	0	0
T92	18803	0	0	0
T93	189706	0	0	0
T94	703922	0	0	0
T95	24698	0	0	0
T96	261261	0	0	0
T97	7789	0	0	0
T98	11923	0	0	0
T99	820664	0	0	0