Unified Coverage Report :: Module :: aon_timer_core

Module : aon_timer_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_core	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : aon_timer_core

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
ALWAYS	46	4	4	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	84	1	1	100.00

40                        // Prescaler counter
41         1/1            assign prescale_count_d = wkup_incr ? 12'h000 : (prescale_count_q + 12'h001);
           Tests:       T1 T2 T3 
42         1/1            assign prescale_en      = reg2hw_i.wkup_ctrl.enable.q &
           Tests:       T1 T2 T3 
43                                                  lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i[0]);
44                      
45                        always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
46         1/1              if (!rst_aon_ni) begin
           Tests:       T1 T2 T3 
47         1/1                prescale_count_q <= 12'h000;
           Tests:       T1 T2 T3 
48         1/1              end else if (prescale_en) begin
           Tests:       T1 T2 T3 
49         1/1                prescale_count_q <= prescale_count_d;
           Tests:       T1 T2 T3 
50                          end
                        MISSING_ELSE
51                        end
52                      
53         1/1            assign wkup_count = {reg2hw_i.wkup_count_hi.q, reg2hw_i.wkup_count_lo.q};
           Tests:       T1 T2 T3 
54         1/1            assign wkup_thold = {reg2hw_i.wkup_thold_hi.q, reg2hw_i.wkup_thold_lo.q};
           Tests:       T1 T2 T3 
55                      
56                        // Wakeup timer count
57         1/1            assign wkup_incr = lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i[1]) &
           Tests:       T1 T2 T3 
58                                           reg2hw_i.wkup_ctrl.enable.q &
59                                           (prescale_count_q == reg2hw_i.wkup_ctrl.prescaler.q);
60                      
61         1/1            assign wkup_count_reg_wr_o  = wkup_incr;
           Tests:       T1 T2 T3 
62         1/1            assign wkup_count_wr_data_o = wkup_count + 64'd1;
           Tests:       T1 T2 T3 
63                      
64                        // Timer interrupt
65         1/1            assign wkup_intr_o = wkup_incr & (wkup_count >= wkup_thold);
           Tests:       T1 T2 T3 
66                      
67                        ////////////////////
68                        // Watchdog Timer //
69                        ////////////////////
70                      
71                        // Watchdog timer count
72         1/1            assign wdog_incr = reg2hw_i.wdog_ctrl.enable.q &
           Tests:       T1 T3 T5 
73                                           lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i[2]) &
74                                           ~(sleep_mode_i & reg2hw_i.wdog_ctrl.pause_in_sleep.q);
75                      
76         1/1            assign wdog_count_reg_wr_o  = wdog_incr;
           Tests:       T5 T7 T13 
77         1/1            assign wdog_count_wr_data_o = (reg2hw_i.wdog_count.q + 32'd1);
           Tests:       T1 T2 T3 
78                      
79                        // Timer interrupt
80         1/1            assign wdog_intr_o = wdog_incr & (reg2hw_i.wdog_count.q >= reg2hw_i.wdog_bark_thold.q);
           Tests:       T1 T2 T3 
81                        // Timer reset
82         1/1            assign wdog_reset_req_o = wdog_incr & (reg2hw_i.wdog_count.q >= reg2hw_i.wdog_bite_thold.q);
           Tests:       T1 T2 T3 
83                      
84         1/1            assign unused_reg2hw = |{reg2hw_i.intr_state, reg2hw_i.intr_test, reg2hw_i.wkup_cause,
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : aon_timer_core

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       41
 EXPRESSION (wkup_incr ? 12'b0 : ((prescale_count_q + 12'b1)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       65
 EXPRESSION (wkup_incr & (wkup_count >= wkup_thold))
             ----1----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (wdog_incr & (reg2hw_i.wdog_count.q >= reg2hw_i.wdog_bark_thold.q))
             ----1----   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T13,T14
1	1	Covered	T13,T14,T26

 LINE       82
 EXPRESSION (wdog_incr & (reg2hw_i.wdog_count.q >= reg2hw_i.wdog_bite_thold.q))
             ----1----   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T13,T14
1	1	Covered	T7,T13,T14

---

Branch Coverage for Module : aon_timer_core

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	41	2	2	100.00
IF	46	3	3	100.00

41           assign prescale_count_d = wkup_incr ? 12'h000 : (prescale_count_q + 12'h001);
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

46             if (!rst_aon_ni) begin
               -1-  
47               prescale_count_q <= 12'h000;
                 ==>
48             end else if (prescale_en) begin
                        -2-  
49               prescale_count_q <= prescale_count_d;
                 ==>
50             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3