Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39064	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

280743

1

T1

12

T2

14

T3

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	81172	1			T1	1		T2	1		T3	1
values[0x0]	113113	1			T1	8		T2	12		T3	9
values[0x1]	125522	1			T1	9		T2	9		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23982	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

295825

1

T1

13

T2

15

T3

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1617	1			T23	11		T24	5		T25	13
valid_sources[0x01]	1063	1			T36	2		T24	1		T25	21
valid_sources[0x02]	1416	1			T7	1		T9	2		T23	2
valid_sources[0x03]	1173	1			T23	11		T24	4		T25	20
valid_sources[0x04]	1110	1			T23	3		T50	1		T24	1
valid_sources[0x05]	1079	1			T1	1		T23	14		T24	6
valid_sources[0x06]	1036	1			T6	2		T23	5		T220	1
valid_sources[0x07]	1021	1			T6	2		T23	14		T86	1
valid_sources[0x08]	1184	1			T1	1		T23	9		T86	1
valid_sources[0x09]	1252	1			T222	1		T23	8		T24	1
valid_sources[0x0a]	1261	1			T23	14		T220	1		T24	2
valid_sources[0x0b]	1507	1			T7	1		T15	1		T223	1
valid_sources[0x0c]	1569	1			T4	1		T17	6		T23	7
valid_sources[0x0d]	994	1			T23	15		T24	1		T25	16
valid_sources[0x0e]	1237	1			T6	1		T15	1		T23	9
valid_sources[0x0f]	1406	1			T7	3		T200	3		T23	19
valid_sources[0x10]	1129	1			T23	11		T53	1		T24	4
valid_sources[0x11]	965	1			T23	9		T220	1		T24	2
valid_sources[0x12]	1107	1			T6	2		T8	1		T23	12
valid_sources[0x13]	949	1			T1	1		T23	11		T24	4
valid_sources[0x14]	1232	1			T4	1		T10	1		T22	1
valid_sources[0x15]	1265	1			T23	14		T24	2		T25	9
valid_sources[0x16]	1351	1			T19	1		T23	10		T224	1
valid_sources[0x17]	1124	1			T34	1		T23	5		T35	1
valid_sources[0x18]	1485	1			T34	1		T23	12		T24	1
valid_sources[0x19]	1106	1			T23	4		T25	15		T30	8
valid_sources[0x1a]	1074	1			T23	1		T86	1		T24	4
valid_sources[0x1b]	1212	1			T200	1		T23	17		T52	12
valid_sources[0x1c]	1189	1			T23	9		T24	6		T25	14
valid_sources[0x1d]	1233	1			T2	1		T10	1		T34	1
valid_sources[0x1e]	1167	1			T200	1		T23	8		T50	1
valid_sources[0x1f]	1006	1			T14	12		T21	1		T23	6
valid_sources[0x20]	1308	1			T23	20		T35	3		T24	1
valid_sources[0x21]	1533	1			T23	7		T24	3		T25	13
valid_sources[0x22]	1137	1			T23	12		T24	3		T25	9
valid_sources[0x23]	933	1			T19	1		T23	2		T24	4
valid_sources[0x24]	1649	1			T2	13		T23	8		T220	1
valid_sources[0x25]	1123	1			T23	1		T86	2		T24	3
valid_sources[0x26]	1364	1			T23	4		T24	3		T25	8
valid_sources[0x27]	1279	1			T200	3		T23	7		T24	6
valid_sources[0x28]	1106	1			T15	1		T23	9		T53	1
valid_sources[0x29]	1397	1			T23	8		T220	1		T24	2
valid_sources[0x2a]	1245	1			T23	16		T24	2		T25	10
valid_sources[0x2b]	1350	1			T19	1		T23	13		T53	1
valid_sources[0x2c]	1177	1			T8	1		T20	22		T34	1
valid_sources[0x2d]	1440	1			T23	20		T24	8		T25	11
valid_sources[0x2e]	1247	1			T23	5		T24	2		T25	15
valid_sources[0x2f]	1139	1			T9	1		T21	2		T23	7
valid_sources[0x30]	1093	1			T23	13		T53	1		T24	2
valid_sources[0x31]	1436	1			T34	1		T23	8		T53	1
valid_sources[0x32]	1138	1			T8	1		T17	1		T23	3
valid_sources[0x33]	1256	1			T23	6		T24	4		T25	7
valid_sources[0x34]	1236	1			T34	2		T223	2		T23	7
valid_sources[0x35]	1376	1			T22	2		T23	7		T24	4
valid_sources[0x36]	1065	1			T34	2		T200	2		T23	7
valid_sources[0x37]	1252	1			T23	4		T220	1		T37	1
valid_sources[0x38]	1277	1			T23	3		T53	1		T24	3
valid_sources[0x39]	1089	1			T222	2		T23	3		T24	3
valid_sources[0x3a]	1481	1			T19	1		T23	6		T86	1
valid_sources[0x3b]	1435	1			T4	2		T10	1		T13	7
valid_sources[0x3c]	1137	1			T23	16		T220	1		T24	1
valid_sources[0x3d]	1452	1			T5	18		T7	2		T23	6
valid_sources[0x3e]	1682	1			T13	1		T23	16		T24	4
valid_sources[0x3f]	1091	1			T8	4		T23	10		T24	7
valid_sources[0x40]	1303	1			T7	1		T23	15		T24	1
valid_sources[0x41]	1295	1			T4	1		T23	13		T220	1
valid_sources[0x42]	2152	1			T23	4		T224	1		T25	11
valid_sources[0x43]	1590	1			T222	2		T23	4		T36	7
valid_sources[0x44]	987	1			T23	12		T24	4		T25	17
valid_sources[0x45]	980	1			T23	7		T36	2		T24	1
valid_sources[0x46]	1155	1			T1	1		T4	1		T8	1
valid_sources[0x47]	1023	1			T21	2		T22	1		T23	3
valid_sources[0x48]	1051	1			T34	1		T23	5		T24	3
valid_sources[0x49]	1107	1			T23	9		T86	1		T24	2
valid_sources[0x4a]	1349	1			T23	11		T53	1		T24	3
valid_sources[0x4b]	1452	1			T9	1		T15	2		T23	5
valid_sources[0x4c]	1023	1			T23	8		T24	4		T25	11
valid_sources[0x4d]	1480	1			T200	2		T23	27		T224	1
valid_sources[0x4e]	1517	1			T21	1		T23	6		T86	1
valid_sources[0x4f]	1004	1			T23	13		T24	2		T25	14
valid_sources[0x50]	1258	1			T3	22		T223	2		T23	8
valid_sources[0x51]	987	1			T23	6		T37	1		T24	2
valid_sources[0x52]	952	1			T1	2		T21	2		T223	1
valid_sources[0x53]	1504	1			T9	1		T17	1		T23	7
valid_sources[0x54]	1056	1			T1	1		T222	1		T23	12
valid_sources[0x55]	1166	1			T15	1		T23	3		T24	6
valid_sources[0x56]	1266	1			T13	1		T223	1		T23	8
valid_sources[0x57]	1203	1			T4	1		T23	12		T224	1
valid_sources[0x58]	1342	1			T7	1		T15	1		T23	5
valid_sources[0x59]	1515	1			T21	1		T23	1		T24	2
valid_sources[0x5a]	1258	1			T7	1		T22	1		T23	11
valid_sources[0x5b]	1217	1			T23	9		T24	4		T25	7
valid_sources[0x5c]	1285	1			T223	1		T23	4		T24	5
valid_sources[0x5d]	1199	1			T23	18		T25	8		T55	2
valid_sources[0x5e]	1335	1			T34	1		T22	1		T23	12
valid_sources[0x5f]	1340	1			T4	1		T10	1		T23	9
valid_sources[0x60]	1473	1			T7	1		T23	13		T24	3
valid_sources[0x61]	1000	1			T23	5		T24	2		T25	15
valid_sources[0x62]	1393	1			T7	1		T10	1		T23	9
valid_sources[0x63]	1363	1			T23	4		T53	1		T24	1
valid_sources[0x64]	982	1			T23	10		T220	1		T24	3
valid_sources[0x65]	1167	1			T2	6		T23	9		T24	2
valid_sources[0x66]	1036	1			T23	21		T37	4		T24	2
valid_sources[0x67]	1570	1			T6	1		T17	3		T223	1
valid_sources[0x68]	1473	1			T19	3		T23	3		T24	3
valid_sources[0x69]	1772	1			T23	10		T50	1		T24	3
valid_sources[0x6a]	1210	1			T4	2		T23	10		T220	1
valid_sources[0x6b]	1345	1			T6	3		T7	1		T23	9
valid_sources[0x6c]	960	1			T24	10		T25	10		T30	4
valid_sources[0x6d]	1160	1			T222	2		T34	1		T23	3
valid_sources[0x6e]	1347	1			T23	12		T24	3		T25	11
valid_sources[0x6f]	1137	1			T23	11		T24	1		T25	18
valid_sources[0x70]	1205	1			T8	1		T23	7		T224	1
valid_sources[0x71]	1752	1			T9	1		T19	2		T23	3
valid_sources[0x72]	1400	1			T6	1		T10	1		T15	1
valid_sources[0x73]	1111	1			T223	1		T23	4		T53	1
valid_sources[0x74]	1505	1			T23	2		T35	10		T24	7
valid_sources[0x75]	1339	1			T7	1		T23	5		T37	1
valid_sources[0x76]	1060	1			T23	7		T24	3		T25	16
valid_sources[0x77]	1446	1			T8	2		T23	7		T37	1
valid_sources[0x78]	1024	1			T17	2		T23	11		T224	1
valid_sources[0x79]	1425	1			T4	1		T23	5		T24	6
valid_sources[0x7a]	1728	1			T8	1		T23	5		T24	2
valid_sources[0x7b]	1469	1			T23	13		T24	4		T25	11
valid_sources[0x7c]	1268	1			T23	11		T36	2		T24	2
valid_sources[0x7d]	1283	1			T21	1		T23	5		T24	4
valid_sources[0x7e]	1006	1			T23	6		T24	6		T25	13
valid_sources[0x7f]	1061	1			T9	2		T23	16		T86	1
valid_sources[0x80]	1062	1			T19	1		T23	6		T225	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

69286

1

T1

1

T3

1

T8

1

values[0x0]

all_enables

biggest_size

105988

1

T1

4

T2

7

T3

6

values[0x1]

all_enables

biggest_size

105469

1

T1

7

T2

7

T3

8