Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	632797275	278234	0	0
wdog_bark_thold_rd_A	632797275	4693	0	0
wdog_bite_thold_rd_A	632797275	4297	0	0
wdog_ctrl_rd_A	632797275	4525	0	0
wdog_regwen_rd_A	632797275	4796	0	0
wkup_ctrl_rd_A	632797275	4740	0	0
wkup_thold_hi_rd_A	632797275	4900	0	0
wkup_thold_lo_rd_A	632797275	4308	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632797275	278234	0	0
T23	65411	2624	0	0
T24	0	502	0	0
T25	0	3131	0	0
T30	0	1330	0	0
T31	0	2956	0	0
T33	407133	0	0	0
T35	38752	0	0	0
T36	17394	0	0	0
T44	365329	0	0	0
T45	0	3828	0	0
T46	0	3286	0	0
T47	0	1197	0	0
T48	0	5864	0	0
T49	0	4247	0	0
T50	9802	0	0	0
T51	14489	0	0	0
T52	21667	0	0	0
T53	289517	0	0	0
T54	400986	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632797275	4693	0	0
T31	104419	0	0	0
T45	177031	381	0	0
T56	738550	0	0	0
T87	0	136	0	0
T88	0	696	0	0
T89	0	229	0	0
T90	0	261	0	0
T91	0	758	0	0
T92	0	206	0	0
T93	0	382	0	0
T94	0	56	0	0
T95	0	255	0	0
T96	3618	0	0	0
T97	40022	0	0	0
T98	10547	0	0	0
T99	576280	0	0	0
T100	52872	0	0	0
T101	39913	0	0	0
T102	902967	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632797275	4297	0	0
T31	104419	0	0	0
T45	177031	380	0	0
T56	738550	0	0	0
T87	0	110	0	0
T88	0	572	0	0
T89	0	268	0	0
T90	0	313	0	0
T91	0	634	0	0
T92	0	155	0	0
T93	0	276	0	0
T94	0	7	0	0
T95	0	275	0	0
T96	3618	0	0	0
T97	40022	0	0	0
T98	10547	0	0	0
T99	576280	0	0	0
T100	52872	0	0	0
T101	39913	0	0	0
T102	902967	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632797275	4525	0	0
T31	104419	0	0	0
T45	177031	396	0	0
T56	738550	0	0	0
T87	0	99	0	0
T88	0	539	0	0
T89	0	243	0	0
T90	0	247	0	0
T91	0	577	0	0
T92	0	167	0	0
T93	0	304	0	0
T94	0	68	0	0
T95	0	273	0	0
T96	3618	0	0	0
T97	40022	0	0	0
T98	10547	0	0	0
T99	576280	0	0	0
T100	52872	0	0	0
T101	39913	0	0	0
T102	902967	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632797275	4796	0	0
T31	104419	0	0	0
T45	177031	329	0	0
T56	738550	0	0	0
T87	0	124	0	0
T88	0	661	0	0
T89	0	264	0	0
T90	0	343	0	0
T91	0	626	0	0
T92	0	191	0	0
T93	0	315	0	0
T94	0	76	0	0
T95	0	217	0	0
T96	3618	0	0	0
T97	40022	0	0	0
T98	10547	0	0	0
T99	576280	0	0	0
T100	52872	0	0	0
T101	39913	0	0	0
T102	902967	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632797275	4740	0	0
T31	104419	0	0	0
T45	177031	357	0	0
T56	738550	0	0	0
T87	0	135	0	0
T88	0	629	0	0
T89	0	261	0	0
T90	0	273	0	0
T91	0	802	0	0
T92	0	185	0	0
T93	0	302	0	0
T94	0	56	0	0
T95	0	189	0	0
T96	3618	0	0	0
T97	40022	0	0	0
T98	10547	0	0	0
T99	576280	0	0	0
T100	52872	0	0	0
T101	39913	0	0	0
T102	902967	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632797275	4900	0	0
T31	104419	0	0	0
T45	177031	461	0	0
T56	738550	0	0	0
T87	0	139	0	0
T88	0	706	0	0
T89	0	357	0	0
T90	0	325	0	0
T91	0	700	0	0
T92	0	236	0	0
T93	0	328	0	0
T94	0	46	0	0
T95	0	249	0	0
T96	3618	0	0	0
T97	40022	0	0	0
T98	10547	0	0	0
T99	576280	0	0	0
T100	52872	0	0	0
T101	39913	0	0	0
T102	902967	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632797275	4308	0	0
T31	104419	0	0	0
T45	177031	357	0	0
T56	738550	0	0	0
T87	0	77	0	0
T88	0	679	0	0
T89	0	210	0	0
T90	0	260	0	0
T91	0	568	0	0
T92	0	102	0	0
T93	0	319	0	0
T94	0	59	0	0
T95	0	226	0	0
T96	3618	0	0	0
T97	40022	0	0	0
T98	10547	0	0	0
T99	576280	0	0	0
T100	52872	0	0	0
T101	39913	0	0	0
T102	902967	0	0	0