Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	20111	1			T1	256		T2	10		T3	10
bark[1]	653	1			T6	14		T26	35		T137	14
bark[2]	228	1			T46	84		T91	21		T189	14
bark[3]	479	1			T45	101		T91	5		T85	56
bark[4]	354	1			T32	75		T91	26		T196	5
bark[5]	560	1			T45	26		T78	7		T150	57
bark[6]	276	1			T23	117		T26	61		T132	21
bark[7]	465	1			T51	14		T46	5		T52	14
bark[8]	263	1			T17	21		T192	61		T170	31
bark[9]	515	1			T20	175		T45	7		T82	7
bark[10]	211	1			T78	5		T154	5		T172	68
bark[11]	227	1			T25	21		T50	14		T115	21
bark[12]	261	1			T25	21		T115	30		T150	54
bark[13]	433	1			T10	14		T32	21		T46	21
bark[14]	365	1			T23	40		T166	14		T47	69
bark[15]	363	1			T19	14		T25	21		T44	30
bark[16]	383	1			T23	26		T32	26		T47	40
bark[17]	334	1			T45	42		T83	5		T133	14
bark[18]	409	1			T25	21		T33	5		T85	21
bark[19]	318	1			T91	21		T186	14		T136	30
bark[20]	486	1			T1	26		T7	14		T23	132
bark[21]	240	1			T4	14		T25	21		T80	30
bark[22]	289	1			T100	14		T145	14		T197	7
bark[23]	282	1			T122	21		T85	21		T164	14
bark[24]	184	1			T14	14		T91	7		T158	14
bark[25]	283	1			T22	14		T30	14		T79	31
bark[26]	417	1			T26	55		T44	7		T91	5
bark[27]	223	1			T198	14		T154	26		T82	7
bark[28]	300	1			T32	7		T188	14		T45	21
bark[29]	338	1			T1	23		T47	48		T123	21
bark[30]	505	1			T25	21		T44	26		T184	14
bark[31]	176	1			T115	42		T159	14		T153	59
bark_0	4780	1			T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	19787	1			T1	256		T2	9		T3	9
bite[1]	348	1			T32	74		T79	4		T150	60
bite[2]	216	1			T198	13		T154	26		T122	12
bite[3]	275	1			T50	13		T46	35		T84	4
bite[4]	409	1			T91	26		T81	13		T85	21
bite[5]	406	1			T14	13		T47	68		T100	13
bite[6]	172	1			T23	13		T44	21		T150	21
bite[7]	481	1			T22	13		T115	30		T159	13
bite[8]	297	1			T1	26		T4	13		T108	13
bite[9]	446	1			T26	35		T51	13		T46	4
bite[10]	629	1			T20	174		T44	25		T91	18
bite[11]	259	1			T6	13		T46	47		T91	4
bite[12]	434	1			T45	6		T140	133		T153	59
bite[13]	273	1			T32	21		T188	13		T122	21
bite[14]	368	1			T30	13		T26	55		T117	38
bite[15]	231	1			T26	40		T47	39		T82	30
bite[16]	324	1			T23	25		T25	21		T33	13
bite[17]	174	1			T44	30		T115	42		T150	25
bite[18]	271	1			T115	21		T85	21		T135	13
bite[19]	411	1			T10	13		T23	26		T33	4
bite[20]	405	1			T79	22		T150	13		T122	145
bite[21]	254	1			T196	4		T144	21		T170	21
bite[22]	554	1			T32	6		T25	21		T189	13
bite[23]	370	1			T23	131		T25	21		T79	26
bite[24]	262	1			T25	21		T45	21		T130	13
bite[25]	141	1			T91	4		T83	4		T190	61
bite[26]	262	1			T7	13		T25	21		T91	21
bite[27]	756	1			T23	116		T32	4		T44	6
bite[28]	90	1			T1	22		T19	13		T25	21
bite[29]	283	1			T45	47		T46	21		T81	25
bite[30]	429	1			T45	100		T166	13		T91	21
bite[31]	399	1			T17	21		T32	26		T147	13
bite_0	5295	1			T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31847

1

T1

312

T2

17

T3

17

auto[1]

3864

1

T15

7

T21

7

T23

131

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	575	1			T1	40		T46	2		T208	9
prescale[1]	608	1			T32	2		T91	2		T79	9
prescale[2]	539	1			T13	9		T25	28		T45	21
prescale[3]	383	1			T16	9		T49	9		T25	23
prescale[4]	569	1			T23	2		T47	2		T79	19
prescale[5]	612	1			T1	23		T8	9		T44	4
prescale[6]	424	1			T1	19		T172	24		T209	9
prescale[7]	372	1			T23	42		T33	2		T44	2
prescale[8]	409	1			T1	24		T32	31		T34	2
prescale[9]	614	1			T23	2		T44	2		T78	9
prescale[10]	451	1			T91	19		T154	36		T157	2
prescale[11]	220	1			T210	9		T132	23		T167	2
prescale[12]	377	1			T17	2		T211	9		T47	2
prescale[13]	575	1			T45	2		T47	2		T154	21
prescale[14]	392	1			T45	2		T91	2		T157	23
prescale[15]	371	1			T45	2		T212	9		T150	2
prescale[16]	376	1			T1	19		T33	2		T34	2
prescale[17]	398	1			T20	2		T34	2		T45	23
prescale[18]	533	1			T20	95		T32	49		T47	2
prescale[19]	499	1			T17	33		T32	2		T78	109
prescale[20]	424	1			T34	2		T53	9		T154	2
prescale[21]	344	1			T32	51		T46	52		T79	2
prescale[22]	314	1			T34	2		T91	2		T213	9
prescale[23]	239	1			T48	9		T45	2		T78	2
prescale[24]	434	1			T20	2		T23	28		T78	2
prescale[25]	228	1			T32	2		T34	2		T47	2
prescale[26]	585	1			T44	2		T150	33		T200	26
prescale[27]	353	1			T23	2		T25	9		T44	2
prescale[28]	343	1			T80	2		T214	9		T157	37
prescale[29]	313	1			T33	2		T34	2		T45	19
prescale[30]	533	1			T20	35		T33	2		T79	12
prescale[31]	518	1			T32	21		T80	2		T122	2
prescale_0	21786	1			T1	187		T2	17		T3	17

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23042

1

T1

172

T2

17

T3

17

auto[1]

12669

1

T1

140

T8

10

T10

12

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

wkup_cause_cleared

35711

1

T1

312

T2

17

T3

17

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	20587	1			T1	236		T2	12		T3	12
wkup[1]	237	1			T6	15		T23	21		T52	15
wkup[2]	84	1			T157	21		T171	21		T94	21
wkup[3]	259	1			T1	26		T20	21		T47	21
wkup[4]	114	1			T150	21		T199	15		T105	21
wkup[5]	134	1			T45	21		T170	30		T99	36
wkup[6]	276	1			T32	21		T45	21		T46	26
wkup[7]	135	1			T46	21		T160	6		T190	35
wkup[8]	99	1			T7	15		T81	21		T120	21
wkup[9]	164	1			T23	42		T91	8		T80	21
wkup[10]	84	1			T91	6		T85	21		T183	15
wkup[11]	249	1			T47	35		T115	21		T79	21
wkup[12]	125	1			T1	21		T181	15		T123	21
wkup[13]	183	1			T122	21		T170	47		T182	21
wkup[14]	150	1			T130	15		T197	21		T170	21
wkup[15]	260	1			T25	21		T26	35		T45	15
wkup[16]	84	1			T10	15		T51	15		T103	15
wkup[17]	278	1			T20	21		T34	26		T188	15
wkup[18]	164	1			T44	21		T92	15		T141	30
wkup[19]	154	1			T154	26		T167	21		T215	8
wkup[20]	199	1			T78	26		T122	21		T85	21
wkup[21]	168	1			T32	21		T78	21		T80	21
wkup[22]	207	1			T140	21		T123	21		T197	21
wkup[23]	186	1			T20	21		T44	21		T79	24
wkup[24]	147	1			T50	15		T47	21		T91	21
wkup[25]	186	1			T19	15		T44	30		T78	21
wkup[26]	182	1			T14	15		T22	15		T195	15
wkup[27]	78	1			T20	15		T176	21		T107	21
wkup[28]	339	1			T1	24		T26	21		T91	26
wkup[29]	222	1			T80	21		T85	30		T172	8
wkup[30]	146	1			T34	26		T154	6		T136	30
wkup[31]	207	1			T46	6		T79	6		T80	21
wkup[32]	299	1			T25	21		T47	26		T153	21
wkup[33]	156	1			T30	15		T81	15		T196	21
wkup[34]	209	1			T102	21		T146	15		T144	21
wkup[35]	177	1			T198	15		T115	21		T171	21
wkup[36]	299	1			T25	42		T45	21		T102	21
wkup[37]	146	1			T45	47		T192	21		T86	15
wkup[38]	123	1			T32	15		T105	21		T136	21
wkup[39]	156	1			T20	21		T115	21		T172	21
wkup[40]	184	1			T32	26		T47	21		T140	21
wkup[41]	226	1			T174	15		T117	21		T170	26
wkup[42]	300	1			T23	30		T25	21		T79	26
wkup[43]	295	1			T23	26		T25	21		T105	21
wkup[44]	221	1			T34	21		T44	21		T115	30
wkup[45]	176	1			T33	15		T47	36		T108	15
wkup[46]	213	1			T85	35		T170	21		T155	26
wkup[47]	190	1			T44	29		T45	8		T144	21
wkup[48]	161	1			T82	30		T170	21		T160	26
wkup[49]	155	1			T32	21		T25	21		T115	21
wkup[50]	206	1			T91	21		T172	35		T173	30
wkup[51]	141	1			T20	21		T23	26		T91	46
wkup[52]	238	1			T4	15		T23	56		T32	30
wkup[53]	141	1			T32	21		T150	21		T123	21
wkup[54]	139	1			T91	26		T115	21		T150	15
wkup[55]	99	1			T171	21		T85	21		T170	21
wkup[56]	295	1			T159	15		T79	21		T81	15
wkup[57]	86	1			T119	15		T170	14		T96	15
wkup[58]	165	1			T26	21		T150	6		T133	15
wkup[59]	150	1			T17	21		T23	15		T111	21
wkup[60]	118	1			T32	8		T33	6		T122	6
wkup[61]	89	1			T78	6		T137	15		T153	21
wkup[62]	134	1			T32	6		T46	21		T78	14
wkup[63]	221	1			T34	30		T166	15		T47	21
wkup_0	3716	1			T1	5		T2	5		T3	5