Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	29632	1		T1	10		T3	10		T5	11
bark[1]	366	1		T18	21		T34	38		T46	31
bark[2]	498	1		T82	21		T115	21		T144	104
bark[3]	411	1		T25	14		T194	14		T22	195
bark[4]	169	1		T4	14		T157	26		T192	40
bark[5]	381	1		T31	14		T196	62		T121	26
bark[6]	687	1		T35	21		T150	47		T124	14
bark[7]	488	1		T126	14		T48	261		T179	7
bark[8]	551	1		T162	21		T23	7		T84	21
bark[9]	793	1		T35	21		T162	14		T48	21
bark[10]	523	1		T9	21		T18	42		T135	14
bark[11]	681	1		T2	14		T9	21		T21	14
bark[12]	453	1		T192	40		T106	14		T109	14
bark[13]	558	1		T193	14		T133	21		T82	254
bark[14]	180	1		T145	14		T45	21		T50	26
bark[15]	505	1		T31	21		T55	14		T162	40
bark[16]	593	1		T21	64		T33	14		T48	213
bark[17]	231	1		T17	26		T189	14		T127	44
bark[18]	494	1		T10	14		T150	21		T126	21
bark[19]	688	1		T17	30		T48	21		T49	7
bark[20]	233	1		T9	21		T18	21		T23	5
bark[21]	444	1		T21	64		T157	26		T196	38
bark[22]	492	1		T44	35		T115	62		T96	33
bark[23]	399	1		T31	35		T51	14		T176	14
bark[24]	371	1		T192	30		T131	81		T142	196
bark[25]	631	1		T9	21		T34	21		T167	14
bark[26]	232	1		T169	14		T174	14		T163	14
bark[27]	1934	1		T34	39		T150	21		T192	30
bark[28]	403	1		T58	14		T174	21		T23	5
bark[29]	375	1		T9	30		T14	14		T41	14
bark[30]	635	1		T9	14		T18	21		T157	40
bark[31]	556	1		T35	35		T22	223		T150	57
bark_0	4725	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	28884	1		T1	9		T3	9		T5	10
bite[1]	540	1		T135	13		T111	13		T48	21
bite[2]	174	1		T9	21		T10	13		T82	21
bite[3]	722	1		T31	21		T35	21		T34	21
bite[4]	204	1		T2	13		T127	40		T174	40
bite[5]	1046	1		T9	30		T124	13		T196	62
bite[6]	460	1		T147	40		T161	21		T125	13
bite[7]	698	1		T32	13		T34	39		T127	21
bite[8]	201	1		T150	21		T157	26		T23	4
bite[9]	626	1		T18	21		T167	13		T186	51
bite[10]	701	1		T194	13		T21	13		T23	6
bite[11]	838	1		T17	30		T31	21		T150	57
bite[12]	477	1		T145	13		T139	13		T174	21
bite[13]	219	1		T9	21		T133	47		T113	21
bite[14]	416	1		T196	38		T141	35		T115	62
bite[15]	207	1		T31	35		T44	35		T110	21
bite[16]	1138	1		T9	21		T31	13		T55	13
bite[17]	400	1		T18	41		T21	63		T162	40
bite[18]	286	1		T14	13		T21	63		T35	21
bite[19]	182	1		T6	13		T41	13		T45	21
bite[20]	212	1		T18	21		T34	38		T169	13
bite[21]	715	1		T58	13		T150	47		T44	191
bite[22]	643	1		T4	13		T50	21		T159	21
bite[23]	981	1		T33	13		T162	13		T163	13
bite[24]	480	1		T189	13		T161	21		T138	13
bite[25]	305	1		T171	74		T156	97		T117	21
bite[26]	850	1		T157	26		T110	42		T151	21
bite[27]	408	1		T9	13		T25	13		T22	194
bite[28]	270	1		T29	13		T35	35		T51	13
bite[29]	601	1		T9	21		T18	21		T196	62
bite[30]	629	1		T17	26		T176	13		T22	222
bite[31]	562	1		T109	13		T49	21		T50	4
bite_0	5237	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	41676	1		T1	17		T2	21		T3	17
auto[1]	8636	1		T5	7		T9	18		T13	7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	994	1		T162	45		T150	23		T44	2
prescale[1]	862	1		T203	9		T44	2		T46	141
prescale[2]	948	1		T9	19		T17	9		T31	23
prescale[3]	1810	1		T204	9		T17	28		T35	14
prescale[4]	988	1		T22	2		T150	9		T192	19
prescale[5]	805	1		T8	9		T162	19		T157	40
prescale[6]	620	1		T18	19		T22	41		T205	9
prescale[7]	914	1		T22	19		T23	60		T46	2
prescale[8]	356	1		T18	18		T22	2		T206	9
prescale[9]	737	1		T18	80		T22	21		T207	9
prescale[10]	1143	1		T9	41		T21	2		T162	19
prescale[11]	621	1		T15	9		T21	2		T162	19
prescale[12]	806	1		T21	2		T35	43		T34	58
prescale[13]	355	1		T208	9		T196	24		T46	53
prescale[14]	833	1		T12	9		T21	53		T22	19
prescale[15]	880	1		T31	19		T209	9		T141	73
prescale[16]	651	1		T16	9		T162	19		T44	61
prescale[17]	610	1		T54	9		T157	24		T23	90
prescale[18]	671	1		T162	19		T210	9		T104	19
prescale[19]	992	1		T18	40		T23	19		T44	175
prescale[20]	699	1		T52	9		T56	9		T44	60
prescale[21]	791	1		T17	53		T211	9		T196	18
prescale[22]	893	1		T162	19		T174	37		T23	33
prescale[23]	622	1		T127	19		T44	156		T50	38
prescale[24]	675	1		T150	40		T212	9		T45	2
prescale[25]	740	1		T59	9		T18	19		T174	28
prescale[26]	557	1		T17	61		T213	9		T127	40
prescale[27]	839	1		T21	2		T214	9		T127	19
prescale[28]	830	1		T23	26		T46	36		T48	201
prescale[29]	894	1		T157	19		T147	63		T48	24
prescale[30]	515	1		T215	9		T162	19		T174	49
prescale[31]	944	1		T60	9		T17	19		T35	28
prescale_0	24717	1		T1	17		T2	21		T3	17

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	37760	1		T1	17		T2	21		T3	17
auto[1]	12552	1		T5	9		T9	151		T12	10

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	50312	1		T1	17		T2	21		T3	17

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	29600	1		T1	12		T2	1		T3	12
wkup[1]	221	1		T174	15		T147	21		T113	30
wkup[2]	155	1		T48	21		T113	21		T182	8
wkup[3]	268	1		T194	15		T31	15		T22	21
wkup[4]	360	1		T44	21		T147	21		T47	21
wkup[5]	257	1		T196	21		T49	35		T193	15
wkup[6]	351	1		T18	21		T162	21		T23	6
wkup[7]	196	1		T41	15		T31	35		T21	15
wkup[8]	188	1		T161	21		T151	21		T128	21
wkup[9]	342	1		T17	21		T18	21		T35	21
wkup[10]	451	1		T23	31		T46	21		T48	31
wkup[11]	114	1		T18	21		T31	21		T144	21
wkup[12]	347	1		T55	15		T145	15		T47	21
wkup[13]	192	1		T22	49		T103	15		T50	21
wkup[14]	197	1		T14	15		T21	21		T126	15
wkup[15]	356	1		T9	21		T47	21		T48	21
wkup[16]	255	1		T35	21		T139	15		T151	21
wkup[17]	368	1		T33	15		T34	39		T150	26
wkup[18]	447	1		T18	21		T32	15		T157	21
wkup[19]	218	1		T196	21		T48	30		T49	21
wkup[20]	296	1		T44	26		T109	15		T49	21
wkup[21]	283	1		T35	35		T44	21		T104	44
wkup[22]	105	1		T21	21		T113	21		T114	21
wkup[23]	357	1		T58	15		T133	21		T50	36
wkup[24]	315	1		T51	15		T196	21		T49	26
wkup[25]	229	1		T29	15		T44	21		T113	21
wkup[26]	225	1		T6	15		T127	21		T45	21
wkup[27]	343	1		T189	15		T22	26		T127	21
wkup[28]	369	1		T150	21		T44	30		T46	21
wkup[29]	242	1		T162	15		T113	21		T118	15
wkup[30]	221	1		T196	21		T45	30		T49	21
wkup[31]	267	1		T17	26		T44	21		T186	21
wkup[32]	98	1		T176	15		T147	26		T47	21
wkup[33]	194	1		T2	15		T161	21		T113	21
wkup[34]	278	1		T169	15		T133	26		T82	21
wkup[35]	230	1		T44	21		T161	21		T179	21
wkup[36]	216	1		T9	30		T150	21		T48	26
wkup[37]	202	1		T35	21		T157	26		T23	6
wkup[38]	225	1		T9	21		T31	21		T22	21
wkup[39]	369	1		T135	15		T44	21		T48	21
wkup[40]	254	1		T25	15		T21	21		T127	44
wkup[41]	358	1		T46	34		T47	21		T48	26
wkup[42]	273	1		T21	21		T34	21		T45	21
wkup[43]	206	1		T48	26		T151	21		T173	15
wkup[44]	293	1		T4	15		T44	21		T151	21
wkup[45]	183	1		T167	15		T192	21		T44	21
wkup[46]	164	1		T9	21		T136	15		T143	30
wkup[47]	134	1		T48	42		T113	21		T90	21
wkup[48]	415	1		T162	21		T45	51		T46	59
wkup[49]	290	1		T9	21		T22	21		T157	21
wkup[50]	246	1		T47	15		T179	21		T182	30
wkup[51]	194	1		T111	15		T45	15		T179	15
wkup[52]	262	1		T150	47		T174	21		T44	26
wkup[53]	272	1		T9	15		T46	21		T126	21
wkup[54]	167	1		T44	21		T45	21		T133	26
wkup[55]	305	1		T23	21		T45	21		T147	21
wkup[56]	242	1		T192	24		T186	21		T82	8
wkup[57]	397	1		T17	30		T196	21		T47	6
wkup[58]	361	1		T46	15		T48	21		T186	21
wkup[59]	280	1		T192	21		T106	15		T46	31
wkup[60]	362	1		T150	21		T192	30		T48	51
wkup[61]	364	1		T10	15		T157	26		T47	30
wkup[62]	339	1		T34	35		T22	21		T141	21
wkup[63]	287	1		T150	21		T192	30		T45	21
wkup_0	3717	1		T1	5		T2	5		T3	5