| | | | | | | |
|
prim_sync_reqack |
87.50 |
100.00 |
50.00 |
|
|
100.00 |
100.00 |
|
tlul_rsp_intg_gen |
91.67 |
83.33 |
|
|
|
|
100.00 |
|
tlul_rsp_intg_gen |
100.00 |
|
|
|
|
|
100.00 |
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) |
66.67 |
66.67 |
|
|
|
|
|
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) |
100.00 |
100.00 |
|
|
|
|
|
|
aon_timer |
92.56 |
96.15 |
66.67 |
100.00 |
|
100.00 |
100.00 |
|
prim_reg_cdc_arb |
98.04 |
100.00 |
96.51 |
|
|
95.65 |
100.00 |
|
prim_reg_cdc_arb |
97.83 |
|
|
|
|
95.65 |
100.00 |
|
prim_reg_cdc_arb ( parameter DataWidth=13,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal=0,DstWrReq=0 + DataWidth=2,ResetVal=0,DstWrReq=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
|
prim_reg_cdc_arb ( parameter DataWidth=32,ResetVal=0,DstWrReq=1 + DataWidth=1,ResetVal=0,DstWrReq=1 ) |
96.51 |
100.00 |
93.02 |
|
|
|
|
|
prim_reg_cdc |
98.33 |
100.00 |
93.30 |
|
|
100.00 |
100.00 |
|
prim_reg_cdc |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
|
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 ) |
93.75 |
|
93.75 |
|
|
|
|
|
prim_reg_cdc ( parameter DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 + DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 ) |
92.86 |
|
92.86 |
|
|
|
|
|
tlul_adapter_reg |
98.98 |
100.00 |
95.92 |
|
|
100.00 |
100.00 |
|
aon_timer_reg_top |
99.57 |
100.00 |
98.28 |
|
|
100.00 |
100.00 |
|
prim_lc_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
|
tlul_data_integ_dec |
100.00 |
100.00 |
|
|
|
|
|
|
aon_timer_core |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
|
tlul_cmd_intg_chk |
100.00 |
100.00 |
|
|
|
|
100.00 |
|
prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
|
prim_edge_detector |
100.00 |
100.00 |
|
|
|
100.00 |
|
|
tlul_assert |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
|
prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
|
prim_subreg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
|
prim_subreg |
100.00 |
100.00 |
|
|
|
100.00 |
|
|
prim_subreg ( parameter DW=1,SwAccess=0,RESVAL=0,Mubi=0 + DW=1,SwAccess=5,RESVAL,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=12,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
aon_timer_csr_assert_fpv |
100.00 |
|
|
|
|
|
100.00 |
|
prim_secded_inv_39_32_dec |
100.00 |
|
|
100.00 |
|
|
|
|
prim_generic_buf |
100.00 |
100.00 |
|
|
|
|
|
|
prim_intr_hw |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
|
prim_pulse_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
|
prim_subreg_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
|
prim_subreg_arb |
100.00 |
|
|
|
|
100.00 |
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=12,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=12,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_ext |
100.00 |
100.00 |
|
|
|
|
|
|
prim_secded_inv_39_32_enc |
100.00 |
100.00 |
|
|
|
|
|
|
tlul_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
|
prim_secded_inv_64_57_enc |
100.00 |
100.00 |
|
|
|
|
|
|
prim_secded_inv_64_57_dec |
100.00 |
|
|
100.00 |
|
|
|
|
prim_generic_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
|
tlul_data_integ_enc |
|
|
|
|
|
|
|
|
prim_reg_we_check |
|
|
|
|
|
|
|
|
prim_buf |
|
|
|
|
|
|
|
|
prim_flop |
|
|
|
|
|
|
|
|
prim_flop_2sync |
|
|
|
|
|
|
|
|
tb |
|
|
|
|
|
|
|
|
prim_sec_anchor_buf |
|
|
|
|
|
|
|