Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.75	99.33	93.67	100.00		98.40	99.51	47.58

Total test records in report: 421

T42	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.687329516	Feb 09 04:10:23 AM UTC 25	Feb 09 04:10:26 AM UTC 25	924618255 ps
T281	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4036178753	Feb 09 04:10:23 AM UTC 25	Feb 09 04:10:26 AM UTC 25	479396772 ps
T43	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.1219967689	Feb 09 04:10:26 AM UTC 25	Feb 09 04:10:28 AM UTC 25	393258309 ps
T37	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1868801967	Feb 09 04:10:27 AM UTC 25	Feb 09 04:10:30 AM UTC 25	1945902834 ps
T38	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1575417781	Feb 09 04:10:27 AM UTC 25	Feb 09 04:10:30 AM UTC 25	411147356 ps
T282	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.2177322284	Feb 09 04:10:29 AM UTC 25	Feb 09 04:10:33 AM UTC 25	494838434 ps
T61	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.176443797	Feb 09 04:10:26 AM UTC 25	Feb 09 04:10:32 AM UTC 25	2955288352 ps
T283	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1015600818	Feb 09 04:10:29 AM UTC 25	Feb 09 04:10:33 AM UTC 25	490985982 ps
T284	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.3253401222	Feb 09 04:10:31 AM UTC 25	Feb 09 04:10:33 AM UTC 25	526538863 ps
T285	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3557002466	Feb 09 04:10:31 AM UTC 25	Feb 09 04:10:33 AM UTC 25	296358849 ps
T286	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2051597395	Feb 09 04:10:32 AM UTC 25	Feb 09 04:10:34 AM UTC 25	444088010 ps
T62	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.3604773807	Feb 09 04:10:33 AM UTC 25	Feb 09 04:10:37 AM UTC 25	499131195 ps
T63	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3991060754	Feb 09 04:10:34 AM UTC 25	Feb 09 04:10:37 AM UTC 25	649622259 ps
T74	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3583738273	Feb 09 04:10:34 AM UTC 25	Feb 09 04:10:37 AM UTC 25	1047335593 ps
T64	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3342833974	Feb 09 04:10:33 AM UTC 25	Feb 09 04:10:38 AM UTC 25	948150690 ps
T216	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4071351597	Feb 09 04:10:35 AM UTC 25	Feb 09 04:10:38 AM UTC 25	425378206 ps
T287	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3823689404	Feb 09 04:10:39 AM UTC 25	Feb 09 04:10:41 AM UTC 25	385457251 ps
T288	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.2774088803	Feb 09 04:10:39 AM UTC 25	Feb 09 04:10:42 AM UTC 25	505739443 ps
T289	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.73370021	Feb 09 04:10:39 AM UTC 25	Feb 09 04:10:42 AM UTC 25	360582361 ps
T290	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.2077534446	Feb 09 04:10:37 AM UTC 25	Feb 09 04:10:44 AM UTC 25	567902538 ps
T291	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3242201177	Feb 09 04:10:33 AM UTC 25	Feb 09 04:10:44 AM UTC 25	14017212959 ps
T292	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.3980629416	Feb 09 04:10:43 AM UTC 25	Feb 09 04:10:46 AM UTC 25	438728401 ps
T65	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.150249640	Feb 09 04:10:44 AM UTC 25	Feb 09 04:10:47 AM UTC 25	527354605 ps
T66	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.892496100	Feb 09 04:10:42 AM UTC 25	Feb 09 04:10:47 AM UTC 25	915025537 ps
T293	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3509790886	Feb 09 04:10:45 AM UTC 25	Feb 09 04:10:48 AM UTC 25	390226464 ps
T294	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.2902699209	Feb 09 04:10:46 AM UTC 25	Feb 09 04:10:50 AM UTC 25	1006303202 ps
T295	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.2340639433	Feb 09 04:10:48 AM UTC 25	Feb 09 04:10:50 AM UTC 25	383095912 ps
T296	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.3585629082	Feb 09 04:10:48 AM UTC 25	Feb 09 04:10:51 AM UTC 25	487770278 ps
T75	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2541725742	Feb 09 04:10:45 AM UTC 25	Feb 09 04:10:51 AM UTC 25	864293164 ps
T297	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1195580827	Feb 09 04:10:49 AM UTC 25	Feb 09 04:10:52 AM UTC 25	503936256 ps
T67	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.2762489832	Feb 09 04:10:50 AM UTC 25	Feb 09 04:10:53 AM UTC 25	467002442 ps
T39	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.952130636	Feb 09 04:10:39 AM UTC 25	Feb 09 04:10:53 AM UTC 25	8811630739 ps
T298	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3236703797	Feb 09 04:10:49 AM UTC 25	Feb 09 04:10:53 AM UTC 25	880875847 ps
T299	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2008070776	Feb 09 04:10:51 AM UTC 25	Feb 09 04:10:54 AM UTC 25	519743055 ps
T300	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1874631684	Feb 09 04:10:51 AM UTC 25	Feb 09 04:10:55 AM UTC 25	448473421 ps
T301	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.2412922933	Feb 09 04:10:53 AM UTC 25	Feb 09 04:10:56 AM UTC 25	300941260 ps
T302	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.504052748	Feb 09 04:10:54 AM UTC 25	Feb 09 04:10:56 AM UTC 25	458949256 ps
T303	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.4234607672	Feb 09 04:10:52 AM UTC 25	Feb 09 04:10:57 AM UTC 25	479304185 ps
T304	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.3123474458	Feb 09 04:10:55 AM UTC 25	Feb 09 04:10:57 AM UTC 25	333428349 ps
T305	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1926315242	Feb 09 04:10:54 AM UTC 25	Feb 09 04:10:57 AM UTC 25	498753408 ps
T76	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3235880723	Feb 09 04:10:51 AM UTC 25	Feb 09 04:10:58 AM UTC 25	2190175296 ps
T306	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3112230603	Feb 09 04:10:56 AM UTC 25	Feb 09 04:10:58 AM UTC 25	563954326 ps
T307	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1924978894	Feb 09 04:10:55 AM UTC 25	Feb 09 04:10:59 AM UTC 25	672839209 ps
T308	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.1691283485	Feb 09 04:10:58 AM UTC 25	Feb 09 04:11:00 AM UTC 25	542780634 ps
T40	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1438291252	Feb 09 04:10:31 AM UTC 25	Feb 09 04:11:00 AM UTC 25	8234540262 ps
T309	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.729720526	Feb 09 04:10:58 AM UTC 25	Feb 09 04:11:01 AM UTC 25	463689414 ps
T310	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2388168094	Feb 09 04:10:58 AM UTC 25	Feb 09 04:11:01 AM UTC 25	396887139 ps
T77	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.2448313282	Feb 09 04:10:58 AM UTC 25	Feb 09 04:11:02 AM UTC 25	384836015 ps
T78	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1413996934	Feb 09 04:10:57 AM UTC 25	Feb 09 04:11:02 AM UTC 25	1160590983 ps
T311	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1809320776	Feb 09 04:10:59 AM UTC 25	Feb 09 04:11:02 AM UTC 25	514612672 ps
T202	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1139770008	Feb 09 04:10:47 AM UTC 25	Feb 09 04:11:08 AM UTC 25	8289480814 ps
T68	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1025176191	Feb 09 04:10:50 AM UTC 25	Feb 09 04:11:03 AM UTC 25	7063103245 ps
T312	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.3700824189	Feb 09 04:11:01 AM UTC 25	Feb 09 04:11:03 AM UTC 25	349162201 ps
T313	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.358659527	Feb 09 04:11:01 AM UTC 25	Feb 09 04:11:03 AM UTC 25	471022117 ps
T314	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.906034472	Feb 09 04:11:00 AM UTC 25	Feb 09 04:11:05 AM UTC 25	483175962 ps
T315	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1769662577	Feb 09 04:11:03 AM UTC 25	Feb 09 04:11:06 AM UTC 25	454997128 ps
T316	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.270101483	Feb 09 04:11:04 AM UTC 25	Feb 09 04:11:06 AM UTC 25	326658378 ps
T79	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2542408678	Feb 09 04:11:03 AM UTC 25	Feb 09 04:11:06 AM UTC 25	1413778874 ps
T317	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.658327537	Feb 09 04:11:03 AM UTC 25	Feb 09 04:11:12 AM UTC 25	8714928579 ps
T80	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2822669630	Feb 09 04:10:59 AM UTC 25	Feb 09 04:11:07 AM UTC 25	2263343285 ps
T318	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.191076457	Feb 09 04:10:53 AM UTC 25	Feb 09 04:11:07 AM UTC 25	8284563971 ps
T319	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.4171714335	Feb 09 04:11:03 AM UTC 25	Feb 09 04:11:07 AM UTC 25	528470186 ps
T73	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.2679572786	Feb 09 04:11:05 AM UTC 25	Feb 09 04:11:08 AM UTC 25	403230727 ps
T81	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3109343229	Feb 09 04:11:05 AM UTC 25	Feb 09 04:11:08 AM UTC 25	2448099476 ps
T320	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4132076401	Feb 09 04:11:06 AM UTC 25	Feb 09 04:11:09 AM UTC 25	360833994 ps
T321	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.1482380214	Feb 09 04:11:06 AM UTC 25	Feb 09 04:11:10 AM UTC 25	1020928569 ps
T322	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3927486307	Feb 09 04:11:01 AM UTC 25	Feb 09 04:11:10 AM UTC 25	8422724615 ps
T323	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.2564946095	Feb 09 04:11:07 AM UTC 25	Feb 09 04:11:10 AM UTC 25	373935572 ps
T69	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.3809548632	Feb 09 04:11:07 AM UTC 25	Feb 09 04:11:11 AM UTC 25	502767778 ps
T324	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3524545424	Feb 09 04:11:07 AM UTC 25	Feb 09 04:11:11 AM UTC 25	1067594966 ps
T325	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3279768645	Feb 09 04:11:08 AM UTC 25	Feb 09 04:11:11 AM UTC 25	416798582 ps
T326	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.3560588927	Feb 09 04:11:09 AM UTC 25	Feb 09 04:11:11 AM UTC 25	393604404 ps
T327	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.2312812196	Feb 09 04:11:09 AM UTC 25	Feb 09 04:11:12 AM UTC 25	593914874 ps
T328	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3518997735	Feb 09 04:10:58 AM UTC 25	Feb 09 04:11:12 AM UTC 25	4689488975 ps
T329	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.3788157371	Feb 09 04:11:10 AM UTC 25	Feb 09 04:11:12 AM UTC 25	527635261 ps
T330	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2956509566	Feb 09 04:11:10 AM UTC 25	Feb 09 04:11:13 AM UTC 25	509040703 ps
T331	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.484762432	Feb 09 04:11:12 AM UTC 25	Feb 09 04:11:14 AM UTC 25	499756851 ps
T70	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.642359830	Feb 09 04:11:12 AM UTC 25	Feb 09 04:11:14 AM UTC 25	450209766 ps
T332	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.1579306223	Feb 09 04:11:13 AM UTC 25	Feb 09 04:11:15 AM UTC 25	390120224 ps
T333	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.563837805	Feb 09 04:11:13 AM UTC 25	Feb 09 04:11:15 AM UTC 25	475241932 ps
T334	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.450236187	Feb 09 04:11:09 AM UTC 25	Feb 09 04:11:15 AM UTC 25	8089391261 ps
T335	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.1981833119	Feb 09 04:11:11 AM UTC 25	Feb 09 04:11:15 AM UTC 25	324196542 ps
T336	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3845545318	Feb 09 04:11:10 AM UTC 25	Feb 09 04:11:16 AM UTC 25	1426201921 ps
T201	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2414738926	Feb 09 04:11:13 AM UTC 25	Feb 09 04:11:16 AM UTC 25	4804175309 ps
T337	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3898696531	Feb 09 04:11:13 AM UTC 25	Feb 09 04:11:16 AM UTC 25	2150528592 ps
T338	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.1226091200	Feb 09 04:11:13 AM UTC 25	Feb 09 04:11:17 AM UTC 25	694873102 ps
T339	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.126242846	Feb 09 04:11:07 AM UTC 25	Feb 09 04:11:17 AM UTC 25	4465378633 ps
T340	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.4014059965	Feb 09 04:11:14 AM UTC 25	Feb 09 04:11:17 AM UTC 25	414380683 ps
T341	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2857980188	Feb 09 04:11:15 AM UTC 25	Feb 09 04:11:18 AM UTC 25	477944095 ps
T342	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.153858300	Feb 09 04:11:16 AM UTC 25	Feb 09 04:11:18 AM UTC 25	292164255 ps
T343	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.1263889322	Feb 09 04:11:16 AM UTC 25	Feb 09 04:11:18 AM UTC 25	452897253 ps
T344	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4173885434	Feb 09 04:10:43 AM UTC 25	Feb 09 04:11:20 AM UTC 25	13780591651 ps
T345	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3983358947	Feb 09 04:11:12 AM UTC 25	Feb 09 04:11:20 AM UTC 25	8663246846 ps
T346	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1412197769	Feb 09 04:11:17 AM UTC 25	Feb 09 04:11:21 AM UTC 25	467690521 ps
T347	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1526910829	Feb 09 04:11:14 AM UTC 25	Feb 09 04:11:21 AM UTC 25	2403877826 ps
T348	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.924597723	Feb 09 04:11:18 AM UTC 25	Feb 09 04:11:21 AM UTC 25	365676742 ps
T349	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.2423739338	Feb 09 04:11:18 AM UTC 25	Feb 09 04:11:21 AM UTC 25	377903251 ps
T350	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.3543232915	Feb 09 04:11:16 AM UTC 25	Feb 09 04:11:21 AM UTC 25	634331932 ps
T351	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.2573252420	Feb 09 04:11:17 AM UTC 25	Feb 09 04:11:21 AM UTC 25	789349673 ps
T352	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2923952902	Feb 09 04:11:17 AM UTC 25	Feb 09 04:11:21 AM UTC 25	4740974374 ps
T353	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3044070216	Feb 09 04:11:17 AM UTC 25	Feb 09 04:11:22 AM UTC 25	2278380965 ps
T354	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3570249101	Feb 09 04:11:18 AM UTC 25	Feb 09 04:11:22 AM UTC 25	1446428644 ps
T355	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2287440184	Feb 09 04:11:20 AM UTC 25	Feb 09 04:11:22 AM UTC 25	285670529 ps
T356	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.3786508440	Feb 09 04:11:21 AM UTC 25	Feb 09 04:11:23 AM UTC 25	398107945 ps
T357	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.1154328943	Feb 09 04:11:20 AM UTC 25	Feb 09 04:11:23 AM UTC 25	647607671 ps
T358	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.95862895	Feb 09 04:11:22 AM UTC 25	Feb 09 04:11:24 AM UTC 25	543378308 ps
T359	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3004904003	Feb 09 04:11:22 AM UTC 25	Feb 09 04:11:25 AM UTC 25	550666015 ps
T360	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.2544961118	Feb 09 04:11:22 AM UTC 25	Feb 09 04:11:25 AM UTC 25	379938800 ps
T361	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2661511578	Feb 09 04:11:22 AM UTC 25	Feb 09 04:11:26 AM UTC 25	4381746846 ps
T362	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.1483854194	Feb 09 04:11:23 AM UTC 25	Feb 09 04:11:26 AM UTC 25	330335997 ps
T363	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.975883032	Feb 09 04:11:21 AM UTC 25	Feb 09 04:11:27 AM UTC 25	7855107119 ps
T364	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.4175385387	Feb 09 04:11:23 AM UTC 25	Feb 09 04:11:27 AM UTC 25	557911595 ps
T365	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.3543142363	Feb 09 04:11:22 AM UTC 25	Feb 09 04:11:27 AM UTC 25	378093488 ps
T366	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.872717950	Feb 09 04:11:22 AM UTC 25	Feb 09 04:11:28 AM UTC 25	1513950957 ps
T367	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.1689663378	Feb 09 04:11:24 AM UTC 25	Feb 09 04:11:28 AM UTC 25	539574724 ps
T368	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.821485817	Feb 09 04:11:24 AM UTC 25	Feb 09 04:11:28 AM UTC 25	424366565 ps
T369	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2126914723	Feb 09 04:11:23 AM UTC 25	Feb 09 04:11:28 AM UTC 25	560915900 ps
T370	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.870147585	Feb 09 04:11:25 AM UTC 25	Feb 09 04:11:28 AM UTC 25	400385955 ps
T371	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.2479135273	Feb 09 04:11:27 AM UTC 25	Feb 09 04:11:29 AM UTC 25	548780520 ps
T372	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3245578301	Feb 09 04:11:23 AM UTC 25	Feb 09 04:11:29 AM UTC 25	4193553692 ps
T71	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.1503995023	Feb 09 04:11:27 AM UTC 25	Feb 09 04:11:29 AM UTC 25	438124718 ps
T373	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.2555811335	Feb 09 04:11:26 AM UTC 25	Feb 09 04:11:30 AM UTC 25	542214361 ps
T374	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3601904120	Feb 09 04:11:24 AM UTC 25	Feb 09 04:11:30 AM UTC 25	1107055703 ps
T375	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3715627451	Feb 09 04:11:23 AM UTC 25	Feb 09 04:11:30 AM UTC 25	1824699467 ps
T376	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1630441948	Feb 09 04:11:28 AM UTC 25	Feb 09 04:11:30 AM UTC 25	1274494077 ps
T377	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1114845044	Feb 09 04:11:28 AM UTC 25	Feb 09 04:11:30 AM UTC 25	704020971 ps
T378	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.1966136206	Feb 09 04:11:28 AM UTC 25	Feb 09 04:11:31 AM UTC 25	620395152 ps
T379	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3229313728	Feb 09 04:11:16 AM UTC 25	Feb 09 04:11:31 AM UTC 25	8418149355 ps
T380	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.2904848738	Feb 09 04:11:29 AM UTC 25	Feb 09 04:11:32 AM UTC 25	282246145 ps
T381	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3658165587	Feb 09 04:11:29 AM UTC 25	Feb 09 04:11:32 AM UTC 25	1381737742 ps
T382	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.2235402177	Feb 09 04:11:29 AM UTC 25	Feb 09 04:11:32 AM UTC 25	527098598 ps
T383	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.123724845	Feb 09 04:11:30 AM UTC 25	Feb 09 04:11:32 AM UTC 25	355985190 ps
T384	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.458223748	Feb 09 04:11:30 AM UTC 25	Feb 09 04:11:33 AM UTC 25	470953267 ps
T385	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.1748819289	Feb 09 04:11:30 AM UTC 25	Feb 09 04:11:33 AM UTC 25	502011385 ps
T386	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1238417618	Feb 09 04:11:29 AM UTC 25	Feb 09 04:11:33 AM UTC 25	546583312 ps
T387	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.3514654208	Feb 09 04:11:31 AM UTC 25	Feb 09 04:11:33 AM UTC 25	476828529 ps
T388	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.60995016	Feb 09 04:11:31 AM UTC 25	Feb 09 04:11:34 AM UTC 25	427192844 ps
T389	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1541437224	Feb 09 04:11:31 AM UTC 25	Feb 09 04:11:34 AM UTC 25	296140114 ps
T390	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2907196871	Feb 09 04:11:26 AM UTC 25	Feb 09 04:11:34 AM UTC 25	4548407296 ps
T391	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.2140265198	Feb 09 04:11:31 AM UTC 25	Feb 09 04:11:34 AM UTC 25	427365251 ps
T392	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.3314529234	Feb 09 04:11:33 AM UTC 25	Feb 09 04:11:35 AM UTC 25	458552465 ps
T393	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.638260003	Feb 09 04:11:33 AM UTC 25	Feb 09 04:11:35 AM UTC 25	411034480 ps
T394	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2181679637	Feb 09 04:11:29 AM UTC 25	Feb 09 04:11:35 AM UTC 25	8486503238 ps
T395	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.761081990	Feb 09 04:11:33 AM UTC 25	Feb 09 04:11:36 AM UTC 25	310084240 ps
T396	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.623734133	Feb 09 04:11:34 AM UTC 25	Feb 09 04:11:36 AM UTC 25	540756579 ps
T397	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.2567737481	Feb 09 04:11:33 AM UTC 25	Feb 09 04:11:36 AM UTC 25	441289615 ps
T398	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.2573530522	Feb 09 04:11:34 AM UTC 25	Feb 09 04:11:36 AM UTC 25	347749706 ps
T399	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.1792315104	Feb 09 04:11:34 AM UTC 25	Feb 09 04:11:37 AM UTC 25	480824159 ps
T400	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.3647116222	Feb 09 04:11:35 AM UTC 25	Feb 09 04:11:37 AM UTC 25	562327684 ps
T401	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.4163733853	Feb 09 04:11:35 AM UTC 25	Feb 09 04:11:38 AM UTC 25	333072981 ps
T402	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.723008201	Feb 09 04:11:34 AM UTC 25	Feb 09 04:11:37 AM UTC 25	430653282 ps
T403	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.1658299844	Feb 09 04:11:35 AM UTC 25	Feb 09 04:11:37 AM UTC 25	291865867 ps
T404	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3361961189	Feb 09 04:11:31 AM UTC 25	Feb 09 04:11:38 AM UTC 25	2124952652 ps
T405	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.3782130707	Feb 09 04:11:35 AM UTC 25	Feb 09 04:11:38 AM UTC 25	389992867 ps
T406	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.456305230	Feb 09 04:11:36 AM UTC 25	Feb 09 04:11:38 AM UTC 25	526586236 ps
T407	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.2008023161	Feb 09 04:11:36 AM UTC 25	Feb 09 04:11:38 AM UTC 25	405457761 ps
T408	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3961349102	Feb 09 04:11:36 AM UTC 25	Feb 09 04:11:39 AM UTC 25	350708080 ps
T409	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2696757295	Feb 09 04:11:35 AM UTC 25	Feb 09 04:11:39 AM UTC 25	496680857 ps
T410	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4024231966	Feb 09 04:11:30 AM UTC 25	Feb 09 04:11:39 AM UTC 25	3921663242 ps
T411	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.71288917	Feb 09 04:11:36 AM UTC 25	Feb 09 04:11:39 AM UTC 25	379196636 ps
T412	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.3129051648	Feb 09 04:11:37 AM UTC 25	Feb 09 04:11:39 AM UTC 25	392130497 ps
T413	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.213679655	Feb 09 04:11:36 AM UTC 25	Feb 09 04:11:40 AM UTC 25	461871282 ps
T414	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.1492600675	Feb 09 04:11:37 AM UTC 25	Feb 09 04:11:40 AM UTC 25	451469553 ps
T415	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.594421454	Feb 09 04:11:37 AM UTC 25	Feb 09 04:11:40 AM UTC 25	335848827 ps
T416	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.4083240310	Feb 09 04:11:37 AM UTC 25	Feb 09 04:11:40 AM UTC 25	353402039 ps
T417	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.927612748	Feb 09 04:11:38 AM UTC 25	Feb 09 04:11:40 AM UTC 25	465384967 ps
T418	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.3828278891	Feb 09 04:11:39 AM UTC 25	Feb 09 04:11:41 AM UTC 25	408047464 ps
T419	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.2607929949	Feb 09 04:11:39 AM UTC 25	Feb 09 04:11:41 AM UTC 25	390702128 ps
T420	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.1785389600	Feb 09 04:11:39 AM UTC 25	Feb 09 04:11:41 AM UTC 25	356360794 ps
T421	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.1632222112	Feb 09 04:11:39 AM UTC 25	Feb 09 04:11:42 AM UTC 25	488403646 ps
T72	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3439676881	Feb 09 04:10:56 AM UTC 25	Feb 09 04:12:07 AM UTC 25	12380037798 ps

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.1108947593
Short name	T8
Test name
Test status
Simulation time	10561246940 ps
CPU time	9.85 seconds
Started	Feb 09 03:54:41 AM UTC 25
Finished	Feb 09 03:54:52 AM UTC 25
Peak memory	200516 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108947593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1108947593
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.2548768116
Short name	T9
Test name
Test status
Simulation time	22892527510 ps
CPU time	12.04 seconds
Started	Feb 09 03:54:40 AM UTC 25
Finished	Feb 09 03:54:53 AM UTC 25
Peak memory	200808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548768116 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.2548768116
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all_with_rand_reset.1550142653
Short name	T44
Test name
Test status
Simulation time	92043525369 ps
CPU time	404.52 seconds
Started	Feb 09 03:54:53 AM UTC 25
Finished	Feb 09 04:01:43 AM UTC 25
Peak memory	223000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550142653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_str ess_all_with_rand_reset.1550142653
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4151897530
Short name	T36
Test name
Test status
Simulation time	8865334107 ps
CPU time	7.31 seconds
Started	Feb 09 04:10:16 AM UTC 25
Finished	Feb 09 04:10:25 AM UTC 25
Peak memory	206920 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151897530 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.4151897530
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all.2516117685
Short name	T34
Test name
Test status
Simulation time	86125148268 ps
CPU time	41.77 seconds
Started	Feb 09 03:57:53 AM UTC 25
Finished	Feb 09 03:58:37 AM UTC 25
Peak memory	200804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516117685 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all.2516117685
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all_with_rand_reset.1247524973
Short name	T134
Test name
Test status
Simulation time	343333320261 ps
CPU time	707.8 seconds
Started	Feb 09 03:58:48 AM UTC 25
Finished	Feb 09 04:10:43 AM UTC 25
Peak memory	222476 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247524973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_st ress_all_with_rand_reset.1247524973
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1575417781
Short name	T38
Test name
Test status
Simulation time	411147356 ps
CPU time	2.18 seconds
Started	Feb 09 04:10:27 AM UTC 25
Finished	Feb 09 04:10:30 AM UTC 25
Peak memory	203068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575417781 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_ timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.1575417781
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all_with_rand_reset.3731512533
Short name	T131
Test name
Test status
Simulation time	57181025447 ps
CPU time	432.18 seconds
Started	Feb 09 04:00:14 AM UTC 25
Finished	Feb 09 04:07:32 AM UTC 25
Peak memory	208856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731512533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_st ress_all_with_rand_reset.3731512533
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.2288170853
Short name	T168
Test name
Test status
Simulation time	74545044678 ps
CPU time	199.8 seconds
Started	Feb 09 04:07:26 AM UTC 25
Finished	Feb 09 04:10:49 AM UTC 25
Peak memory	201060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288170853 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.2288170853
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/42.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all_with_rand_reset.447951190
Short name	T116
Test name
Test status
Simulation time	228364919667 ps
CPU time	339.23 seconds
Started	Feb 09 04:03:59 AM UTC 25
Finished	Feb 09 04:09:42 AM UTC 25
Peak memory	221644 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447951190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_str ess_all_with_rand_reset.447951190
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all_with_rand_reset.1596170746
Short name	T143
Test name
Test status
Simulation time	232252424543 ps
CPU time	690.52 seconds
Started	Feb 09 03:55:43 AM UTC 25
Finished	Feb 09 04:07:21 AM UTC 25
Peak memory	217404 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596170746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_str ess_all_with_rand_reset.1596170746
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.2583342041
Short name	T11
Test name
Test status
Simulation time	4432057689 ps
CPU time	7.57 seconds
Started	Feb 09 03:54:38 AM UTC 25
Finished	Feb 09 03:54:47 AM UTC 25
Peak memory	231828 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583342041 -assert nopostproc +UVM_TESTNAME=aon_timer_ba se_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2583342041
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all_with_rand_reset.2606352339
Short name	T94
Test name
Test status
Simulation time	73272537446 ps
CPU time	656.64 seconds
Started	Feb 09 04:05:21 AM UTC 25
Finished	Feb 09 04:16:25 AM UTC 25
Peak memory	212824 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606352339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_st ress_all_with_rand_reset.2606352339
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/35.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all_with_rand_reset.3473772296
Short name	T50
Test name
Test status
Simulation time	35684387462 ps
CPU time	407.78 seconds
Started	Feb 09 03:58:23 AM UTC 25
Finished	Feb 09 04:05:16 AM UTC 25
Peak memory	221780 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473772296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_st ress_all_with_rand_reset.3473772296
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all_with_rand_reset.4072444047
Short name	T142
Test name
Test status
Simulation time	47422696278 ps
CPU time	484.35 seconds
Started	Feb 09 04:00:34 AM UTC 25
Finished	Feb 09 04:08:44 AM UTC 25
Peak memory	215420 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072444047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_st ress_all_with_rand_reset.4072444047
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.3673948188
Short name	T48
Test name
Test status
Simulation time	129008244312 ps
CPU time	460.08 seconds
Started	Feb 09 03:55:56 AM UTC 25
Finished	Feb 09 04:03:42 AM UTC 25
Peak memory	210728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673948188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_str ess_all_with_rand_reset.3673948188
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all.1247501057
Short name	T151
Test name
Test status
Simulation time	3827847749 ps
CPU time	7.25 seconds
Started	Feb 09 04:03:52 AM UTC 25
Finished	Feb 09 04:04:01 AM UTC 25
Peak memory	200804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247501057 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all.1247501057
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/30.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all_with_rand_reset.2777036424
Short name	T119
Test name
Test status
Simulation time	136441019132 ps
CPU time	774.36 seconds
Started	Feb 09 04:08:09 AM UTC 25
Finished	Feb 09 04:21:12 AM UTC 25
Peak memory	223084 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777036424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_st ress_all_with_rand_reset.2777036424
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/44.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.3296313270
Short name	T166
Test name
Test status
Simulation time	410848409251 ps
CPU time	1002.77 seconds
Started	Feb 09 04:03:52 AM UTC 25
Finished	Feb 09 04:20:47 AM UTC 25
Peak memory	222996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296313270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_st ress_all_with_rand_reset.3296313270
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all.3574426478
Short name	T17
Test name
Test status
Simulation time	585833462858 ps
CPU time	84.56 seconds
Started	Feb 09 03:55:30 AM UTC 25
Finished	Feb 09 03:56:57 AM UTC 25
Peak memory	200736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574426478 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all.3574426478
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all_with_rand_reset.3504795767
Short name	T100
Test name
Test status
Simulation time	173186441426 ps
CPU time	820.11 seconds
Started	Feb 09 03:59:26 AM UTC 25
Finished	Feb 09 04:13:16 AM UTC 25
Peak memory	213520 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504795767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_st ress_all_with_rand_reset.3504795767
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.1868724209
Short name	T82
Test name
Test status
Simulation time	165656557544 ps
CPU time	610.94 seconds
Started	Feb 09 03:55:21 AM UTC 25
Finished	Feb 09 04:05:39 AM UTC 25
Peak memory	221588 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868724209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_str ess_all_with_rand_reset.1868724209
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.405357312
Short name	T132
Test name
Test status
Simulation time	123694094268 ps
CPU time	539.1 seconds
Started	Feb 09 04:02:17 AM UTC 25
Finished	Feb 09 04:11:23 AM UTC 25
Peak memory	221840 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405357312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_str ess_all_with_rand_reset.405357312
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.1435712765
Short name	T112
Test name
Test status
Simulation time	143634061392 ps
CPU time	108.95 seconds
Started	Feb 09 04:04:14 AM UTC 25
Finished	Feb 09 04:06:05 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435712765 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.1435712765
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/32.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all_with_rand_reset.2326145409
Short name	T156
Test name
Test status
Simulation time	118972715100 ps
CPU time	252.43 seconds
Started	Feb 09 04:04:28 AM UTC 25
Finished	Feb 09 04:08:44 AM UTC 25
Peak memory	217720 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326145409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_st ress_all_with_rand_reset.2326145409
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.1072798315
Short name	T170
Test name
Test status
Simulation time	213331263896 ps
CPU time	429.58 seconds
Started	Feb 09 04:05:38 AM UTC 25
Finished	Feb 09 04:12:53 AM UTC 25
Peak memory	200944 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072798315 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.1072798315
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/36.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.3439013107
Short name	T172
Test name
Test status
Simulation time	168495435981 ps
CPU time	271.44 seconds
Started	Feb 09 04:09:51 AM UTC 25
Finished	Feb 09 04:14:26 AM UTC 25
Peak memory	200804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439013107 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.3439013107
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/48.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all.961678929
Short name	T123
Test name
Test status
Simulation time	238023382526 ps
CPU time	482.27 seconds
Started	Feb 09 04:05:51 AM UTC 25
Finished	Feb 09 04:13:59 AM UTC 25
Peak memory	200808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961678929 -assert nopostproc +UVM_TESTNAME=aon_timer _base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ao n_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.961678929
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/38.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.2427704319
Short name	T117
Test name
Test status
Simulation time	88957663182 ps
CPU time	246.09 seconds
Started	Feb 09 04:06:16 AM UTC 25
Finished	Feb 09 04:10:25 AM UTC 25
Peak memory	200804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427704319 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.2427704319
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/40.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all_with_rand_reset.324957770
Short name	T183
Test name
Test status
Simulation time	56137323089 ps
CPU time	457.76 seconds
Started	Feb 09 04:03:07 AM UTC 25
Finished	Feb 09 04:10:50 AM UTC 25
Peak memory	219584 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324957770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_str ess_all_with_rand_reset.324957770
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all.1458525185
Short name	T114
Test name
Test status
Simulation time	30113334192 ps
CPU time	47.18 seconds
Started	Feb 09 04:07:13 AM UTC 25
Finished	Feb 09 04:08:02 AM UTC 25
Peak memory	200996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458525185 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all.1458525185
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/41.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all_with_rand_reset.4042520893
Short name	T113
Test name
Test status
Simulation time	39116210272 ps
CPU time	457.15 seconds
Started	Feb 09 03:57:51 AM UTC 25
Finished	Feb 09 04:05:34 AM UTC 25
Peak memory	217476 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042520893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_st ress_all_with_rand_reset.4042520893
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all_with_rand_reset.174584311
Short name	T97
Test name
Test status
Simulation time	59857003067 ps
CPU time	490.32 seconds
Started	Feb 09 04:02:41 AM UTC 25
Finished	Feb 09 04:10:58 AM UTC 25
Peak memory	217680 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174584311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_str ess_all_with_rand_reset.174584311
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all_with_rand_reset.1384035545
Short name	T181
Test name
Test status
Simulation time	82702864880 ps
CPU time	813.94 seconds
Started	Feb 09 04:03:16 AM UTC 25
Finished	Feb 09 04:16:59 AM UTC 25
Peak memory	212988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384035545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_st ress_all_with_rand_reset.1384035545
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.198764803
Short name	T188
Test name
Test status
Simulation time	89848812288 ps
CPU time	208.06 seconds
Started	Feb 09 04:06:02 AM UTC 25
Finished	Feb 09 04:09:33 AM UTC 25
Peak memory	222884 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198764803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_str ess_all_with_rand_reset.198764803
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all_with_rand_reset.611710658
Short name	T144
Test name
Test status
Simulation time	179568850590 ps
CPU time	913.86 seconds
Started	Feb 09 03:54:44 AM UTC 25
Finished	Feb 09 04:10:09 AM UTC 25
Peak memory	222844 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611710658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stre ss_all_with_rand_reset.611710658
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.402461213
Short name	T147
Test name
Test status
Simulation time	92194255499 ps
CPU time	76.95 seconds
Started	Feb 09 04:02:06 AM UTC 25
Finished	Feb 09 04:03:25 AM UTC 25
Peak memory	200736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402461213 -assert nopostproc +UVM_TESTNAME=aon_timer _base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ao n_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.402461213
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/24.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all.486151503
Short name	T129
Test name
Test status
Simulation time	187643552472 ps
CPU time	421.2 seconds
Started	Feb 09 04:03:45 AM UTC 25
Finished	Feb 09 04:10:51 AM UTC 25
Peak memory	201000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486151503 -assert nopostproc +UVM_TESTNAME=aon_timer _base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ao n_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all.486151503
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/29.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.2831524693
Short name	T133
Test name
Test status
Simulation time	15151658340 ps
CPU time	29 seconds
Started	Feb 09 04:04:01 AM UTC 25
Finished	Feb 09 04:04:31 AM UTC 25
Peak memory	200732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831524693 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.2831524693
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/31.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all.2370276670
Short name	T127
Test name
Test status
Simulation time	261209375946 ps
CPU time	137.43 seconds
Started	Feb 09 03:58:13 AM UTC 25
Finished	Feb 09 04:00:32 AM UTC 25
Peak memory	200732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370276670 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all.2370276670
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all.1708073363
Short name	T161
Test name
Test status
Simulation time	253158902815 ps
CPU time	167.05 seconds
Started	Feb 09 04:01:10 AM UTC 25
Finished	Feb 09 04:04:00 AM UTC 25
Peak memory	200996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708073363 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all.1708073363
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/22.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all_with_rand_reset.258433054
Short name	T101
Test name
Test status
Simulation time	65130062979 ps
CPU time	546.24 seconds
Started	Feb 09 04:05:38 AM UTC 25
Finished	Feb 09 04:14:52 AM UTC 25
Peak memory	219656 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258433054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_str ess_all_with_rand_reset.258433054
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.1265405184
Short name	T182
Test name
Test status
Simulation time	157857474874 ps
CPU time	552.34 seconds
Started	Feb 09 03:59:03 AM UTC 25
Finished	Feb 09 04:08:22 AM UTC 25
Peak memory	221560 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265405184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_st ress_all_with_rand_reset.1265405184
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all_with_rand_reset.2196914276
Short name	T128
Test name
Test status
Simulation time	28820609809 ps
CPU time	125.68 seconds
Started	Feb 09 04:05:04 AM UTC 25
Finished	Feb 09 04:07:12 AM UTC 25
Peak memory	214284 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196914276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_st ress_all_with_rand_reset.2196914276
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all_with_rand_reset.506803529
Short name	T140
Test name
Test status
Simulation time	47981392214 ps
CPU time	173.32 seconds
Started	Feb 09 04:09:07 AM UTC 25
Finished	Feb 09 04:12:03 AM UTC 25
Peak memory	206868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506803529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_str ess_all_with_rand_reset.506803529
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/47.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.3190279727
Short name	T29
Test name
Test status
Simulation time	556443006 ps
CPU time	2.62 seconds
Started	Feb 09 03:56:25 AM UTC 25
Finished	Feb 09 03:56:29 AM UTC 25
Peak memory	200872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190279727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 8.aon_timer_jump.3190279727
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all_with_rand_reset.2936167431
Short name	T146
Test name
Test status
Simulation time	280802428213 ps
CPU time	971.92 seconds
Started	Feb 09 03:58:36 AM UTC 25
Finished	Feb 09 04:15:00 AM UTC 25
Peak memory	223052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936167431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_st ress_all_with_rand_reset.2936167431
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all.489438623
Short name	T90
Test name
Test status
Simulation time	10398459992 ps
CPU time	6.05 seconds
Started	Feb 09 04:05:43 AM UTC 25
Finished	Feb 09 04:05:51 AM UTC 25
Peak memory	200744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489438623 -assert nopostproc +UVM_TESTNAME=aon_timer _base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ao n_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all.489438623
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/37.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all.4286686182
Short name	T84
Test name
Test status
Simulation time	118153822404 ps
CPU time	17.62 seconds
Started	Feb 09 04:05:24 AM UTC 25
Finished	Feb 09 04:05:43 AM UTC 25
Peak memory	200804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286686182 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all.4286686182
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/35.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.1995515238
Short name	T22
Test name
Test status
Simulation time	165888625307 ps
CPU time	118.41 seconds
Started	Feb 09 03:56:55 AM UTC 25
Finished	Feb 09 03:58:56 AM UTC 25
Peak memory	217464 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995515238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_str ess_all_with_rand_reset.1995515238
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.2418034112
Short name	T45
Test name
Test status
Simulation time	124370739935 ps
CPU time	278.65 seconds
Started	Feb 09 03:57:26 AM UTC 25
Finished	Feb 09 04:02:09 AM UTC 25
Peak memory	208656 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418034112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_st ress_all_with_rand_reset.2418034112
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all.4079144033
Short name	T157
Test name
Test status
Simulation time	163800396838 ps
CPU time	321.12 seconds
Started	Feb 09 03:54:44 AM UTC 25
Finished	Feb 09 04:00:09 AM UTC 25
Peak memory	200620 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079144033 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.4079144033
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all.3878279425
Short name	T153
Test name
Test status
Simulation time	164381498281 ps
CPU time	241.31 seconds
Started	Feb 09 04:06:06 AM UTC 25
Finished	Feb 09 04:10:10 AM UTC 25
Peak memory	200996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878279425 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all.3878279425
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/39.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all_with_rand_reset.1640511206
Short name	T96
Test name
Test status
Simulation time	25987574073 ps
CPU time	185.95 seconds
Started	Feb 09 04:06:48 AM UTC 25
Finished	Feb 09 04:09:57 AM UTC 25
Peak memory	206572 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640511206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_st ress_all_with_rand_reset.1640511206
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/41.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all_with_rand_reset.1616052823
Short name	T99
Test name
Test status
Simulation time	46041266298 ps
CPU time	343.91 seconds
Started	Feb 09 04:07:24 AM UTC 25
Finished	Feb 09 04:13:13 AM UTC 25
Peak memory	219504 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616052823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_st ress_all_with_rand_reset.1616052823
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all.1643430848
Short name	T120
Test name
Test status
Simulation time	200944618247 ps
CPU time	266.79 seconds
Started	Feb 09 04:08:16 AM UTC 25
Finished	Feb 09 04:12:47 AM UTC 25
Peak memory	200732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643430848 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all.1643430848
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/44.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.808957429
Short name	T150
Test name
Test status
Simulation time	43941250435 ps
CPU time	34.15 seconds
Started	Feb 09 03:58:37 AM UTC 25
Finished	Feb 09 03:59:13 AM UTC 25
Peak memory	200744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808957429 -assert nopostproc +UVM_TESTNAME=aon_timer _base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ao n_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all.808957429
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.176443797
Short name	T61
Test name
Test status
Simulation time	2955288352 ps
CPU time	5.68 seconds
Started	Feb 09 04:10:26 AM UTC 25
Finished	Feb 09 04:10:32 AM UTC 25
Peak memory	205300 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176443797 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.176443797
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1868801967
Short name	T37
Test name
Test status
Simulation time	1945902834 ps
CPU time	1.7 seconds
Started	Feb 09 04:10:27 AM UTC 25
Finished	Feb 09 04:10:30 AM UTC 25
Peak memory	204340 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868801967 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.1868801967
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.3863676153
Short name	T162
Test name
Test status
Simulation time	207153315624 ps
CPU time	80.85 seconds
Started	Feb 09 03:57:29 AM UTC 25
Finished	Feb 09 03:58:52 AM UTC 25
Peak memory	200804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863676153 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.3863676153
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.1870899011
Short name	T110
Test name
Test status
Simulation time	325735976287 ps
CPU time	320.98 seconds
Started	Feb 09 03:58:26 AM UTC 25
Finished	Feb 09 04:03:51 AM UTC 25
Peak memory	200732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870899011 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.1870899011
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.2361755856
Short name	T177
Test name
Test status
Simulation time	503895991235 ps
CPU time	833.37 seconds
Started	Feb 09 03:54:54 AM UTC 25
Finished	Feb 09 04:08:56 AM UTC 25
Peak memory	200872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361755856 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.2361755856
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.2756123686
Short name	T158
Test name
Test status
Simulation time	287466837778 ps
CPU time	344.03 seconds
Started	Feb 09 04:05:09 AM UTC 25
Finished	Feb 09 04:10:57 AM UTC 25
Peak memory	200804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756123686 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.2756123686
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/34.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.2305826903
Short name	T18
Test name
Test status
Simulation time	276106777475 ps
CPU time	124.59 seconds
Started	Feb 09 03:55:06 AM UTC 25
Finished	Feb 09 03:57:13 AM UTC 25
Peak memory	201064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305826903 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.2305826903
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all_with_rand_reset.3692691293
Short name	T102
Test name
Test status
Simulation time	68095231740 ps
CPU time	309.78 seconds
Started	Feb 09 04:10:09 AM UTC 25
Finished	Feb 09 04:15:23 AM UTC 25
Peak memory	217496 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692691293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_st ress_all_with_rand_reset.3692691293
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.1332155666
Short name	T192
Test name
Test status
Simulation time	234888453439 ps
CPU time	331.24 seconds
Started	Feb 09 03:56:03 AM UTC 25
Finished	Feb 09 04:01:39 AM UTC 25
Peak memory	200736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332155666 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.1332155666
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all.1060021251
Short name	T196
Test name
Test status
Simulation time	84876988130 ps
CPU time	160.89 seconds
Started	Feb 09 03:58:53 AM UTC 25
Finished	Feb 09 04:01:36 AM UTC 25
Peak memory	200804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060021251 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.1060021251
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all.2992899911
Short name	T152
Test name
Test status
Simulation time	544221103291 ps
CPU time	1062.4 seconds
Started	Feb 09 03:59:09 AM UTC 25
Finished	Feb 09 04:17:02 AM UTC 25
Peak memory	200996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992899911 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.2992899911
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/16.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all_with_rand_reset.89464575
Short name	T93
Test name
Test status
Simulation time	203440875292 ps
CPU time	477.66 seconds
Started	Feb 09 04:03:42 AM UTC 25
Finished	Feb 09 04:11:46 AM UTC 25
Peak memory	219704 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89464575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stre ss_all_with_rand_reset.89464575
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all_with_rand_reset.1372684301
Short name	T98
Test name
Test status
Simulation time	21525557894 ps
CPU time	186.43 seconds
Started	Feb 09 04:08:47 AM UTC 25
Finished	Feb 09 04:11:57 AM UTC 25
Peak memory	213972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372684301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_st ress_all_with_rand_reset.1372684301
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/46.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.3185999318
Short name	T35
Test name
Test status
Simulation time	88639629972 ps
CPU time	209.11 seconds
Started	Feb 09 03:54:37 AM UTC 25
Finished	Feb 09 03:58:09 AM UTC 25
Peak memory	201000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185999318 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.3185999318
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.1994302143
Short name	T51
Test name
Test status
Simulation time	400071485 ps
CPU time	1.97 seconds
Started	Feb 09 03:58:07 AM UTC 25
Finished	Feb 09 03:58:11 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994302143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 12.aon_timer_jump.1994302143
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.4138193232
Short name	T167
Test name
Test status
Simulation time	443629890 ps
CPU time	1.1 seconds
Started	Feb 09 03:59:50 AM UTC 25
Finished	Feb 09 03:59:52 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138193232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 18.aon_timer_jump.4138193232
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.3779786688
Short name	T165
Test name
Test status
Simulation time	488021246 ps
CPU time	1.15 seconds
Started	Feb 09 04:03:49 AM UTC 25
Finished	Feb 09 04:03:51 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779786688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 30.aon_timer_jump.3779786688
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/30.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all_with_rand_reset.1718659632
Short name	T195
Test name
Test status
Simulation time	119457618178 ps
CPU time	482.04 seconds
Started	Feb 09 04:04:08 AM UTC 25
Finished	Feb 09 04:12:15 AM UTC 25
Peak memory	221592 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718659632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_st ress_all_with_rand_reset.1718659632
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.1215598108
Short name	T179
Test name
Test status
Simulation time	98813823337 ps
CPU time	249.15 seconds
Started	Feb 09 04:01:24 AM UTC 25
Finished	Feb 09 04:05:37 AM UTC 25
Peak memory	208976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215598108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_st ress_all_with_rand_reset.1215598108
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all.2113588143
Short name	T141
Test name
Test status
Simulation time	53274849829 ps
CPU time	30.75 seconds
Started	Feb 09 04:02:30 AM UTC 25
Finished	Feb 09 04:03:02 AM UTC 25
Peak memory	200996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113588143 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all.2113588143
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/25.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.1133448431
Short name	T125
Test name
Test status
Simulation time	363793736 ps
CPU time	1.33 seconds
Started	Feb 09 04:04:05 AM UTC 25
Finished	Feb 09 04:04:07 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133448431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 32.aon_timer_jump.1133448431
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/32.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.2515033920
Short name	T137
Test name
Test status
Simulation time	402856136 ps
CPU time	1.11 seconds
Started	Feb 09 04:05:21 AM UTC 25
Finished	Feb 09 04:05:23 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515033920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 35.aon_timer_jump.2515033920
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/35.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all_with_rand_reset.2828530125
Short name	T92
Test name
Test status
Simulation time	20680520944 ps
CPU time	281.01 seconds
Started	Feb 09 04:05:42 AM UTC 25
Finished	Feb 09 04:10:28 AM UTC 25
Peak memory	206860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828530125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_st ress_all_with_rand_reset.2828530125
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all_with_rand_reset.2740504296
Short name	T95
Test name
Test status
Simulation time	102657037964 ps
CPU time	453.22 seconds
Started	Feb 09 04:09:48 AM UTC 25
Finished	Feb 09 04:17:27 AM UTC 25
Peak memory	219704 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740504296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_st ress_all_with_rand_reset.2740504296
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all.3734549754
Short name	T187
Test name
Test status
Simulation time	68006619672 ps
CPU time	18.24 seconds
Started	Feb 09 04:10:11 AM UTC 25
Finished	Feb 09 04:10:31 AM UTC 25
Peak memory	200732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734549754 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all.3734549754
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/49.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.24907906
Short name	T33
Test name
Test status
Simulation time	494792461 ps
CPU time	1.64 seconds
Started	Feb 09 03:58:33 AM UTC 25
Finished	Feb 09 03:58:36 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24907906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_t imer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.24907906
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.3978760597
Short name	T139
Test name
Test status
Simulation time	544776055 ps
CPU time	3.06 seconds
Started	Feb 09 03:59:25 AM UTC 25
Finished	Feb 09 03:59:30 AM UTC 25
Peak memory	200808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978760597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 17.aon_timer_jump.3978760597
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all.3610403127
Short name	T149
Test name
Test status
Simulation time	333577790930 ps
CPU time	299.85 seconds
Started	Feb 09 04:00:16 AM UTC 25
Finished	Feb 09 04:05:20 AM UTC 25
Peak memory	200804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610403127 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all.3610403127
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.1290361291
Short name	T126
Test name
Test status
Simulation time	206325108035 ps
CPU time	164.93 seconds
Started	Feb 09 04:00:26 AM UTC 25
Finished	Feb 09 04:03:14 AM UTC 25
Peak memory	200732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290361291 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.1290361291
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/20.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all_with_rand_reset.646898776
Short name	T171
Test name
Test status
Simulation time	52720168984 ps
CPU time	412.55 seconds
Started	Feb 09 04:01:06 AM UTC 25
Finished	Feb 09 04:08:04 AM UTC 25
Peak memory	217564 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646898776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_str ess_all_with_rand_reset.646898776
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.3313553660
Short name	T186
Test name
Test status
Simulation time	107368010627 ps
CPU time	56.15 seconds
Started	Feb 09 04:02:47 AM UTC 25
Finished	Feb 09 04:03:45 AM UTC 25
Peak memory	200732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313553660 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all.3313553660
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.1840380996
Short name	T138
Test name
Test status
Simulation time	527774399 ps
CPU time	1.36 seconds
Started	Feb 09 04:05:01 AM UTC 25
Finished	Feb 09 04:05:04 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840380996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 34.aon_timer_jump.1840380996
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/34.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.1834458935
Short name	T130
Test name
Test status
Simulation time	109238601476 ps
CPU time	96.71 seconds
Started	Feb 09 04:09:10 AM UTC 25
Finished	Feb 09 04:10:48 AM UTC 25
Peak memory	200868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834458935 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.1834458935
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/47.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.3140105468
Short name	T145
Test name
Test status
Simulation time	496849464 ps
CPU time	2.62 seconds
Started	Feb 09 03:58:59 AM UTC 25
Finished	Feb 09 03:59:03 AM UTC 25
Peak memory	200872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140105468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 16.aon_timer_jump.3140105468
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/16.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.707394504
Short name	T163
Test name
Test status
Simulation time	501508186 ps
CPU time	1.78 seconds
Started	Feb 09 04:01:20 AM UTC 25
Finished	Feb 09 04:01:23 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707394504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 23.aon_timer_jump.707394504
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/23.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.4169680719
Short name	T103
Test name
Test status
Simulation time	352517026 ps
CPU time	1.28 seconds
Started	Feb 09 04:01:44 AM UTC 25
Finished	Feb 09 04:01:46 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169680719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 24.aon_timer_jump.4169680719
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/24.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.4100602698
Short name	T136
Test name
Test status
Simulation time	499087401 ps
CPU time	2.31 seconds
Started	Feb 09 04:03:03 AM UTC 25
Finished	Feb 09 04:03:06 AM UTC 25
Peak memory	200604 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100602698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 27.aon_timer_jump.4100602698
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.1323398578
Short name	T21
Test name
Test status
Simulation time	17734056463 ps
CPU time	176.64 seconds
Started	Feb 09 03:55:06 AM UTC 25
Finished	Feb 09 03:58:06 AM UTC 25
Peak memory	215548 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323398578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_str ess_all_with_rand_reset.1323398578
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.2323971505
Short name	T118
Test name
Test status
Simulation time	553187542 ps
CPU time	1.44 seconds
Started	Feb 09 04:06:45 AM UTC 25
Finished	Feb 09 04:06:47 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323971505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 41.aon_timer_jump.2323971505
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/41.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all.2585824328
Short name	T175
Test name
Test status
Simulation time	501873188745 ps
CPU time	692.73 seconds
Started	Feb 09 04:08:39 AM UTC 25
Finished	Feb 09 04:20:19 AM UTC 25
Peak memory	200804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585824328 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all.2585824328
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/45.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.2519173985
Short name	T31
Test name
Test status
Simulation time	26023555107 ps
CPU time	67.34 seconds
Started	Feb 09 03:56:36 AM UTC 25
Finished	Feb 09 03:57:45 AM UTC 25
Peak memory	200732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519173985 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.2519173985
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.1256252614
Short name	T55
Test name
Test status
Simulation time	657665166 ps
CPU time	0.93 seconds
Started	Feb 09 03:58:19 AM UTC 25
Finished	Feb 09 03:58:21 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256252614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 13.aon_timer_jump.1256252614
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.1149355116
Short name	T135
Test name
Test status
Simulation time	563549054 ps
CPU time	1.83 seconds
Started	Feb 09 04:00:12 AM UTC 25
Finished	Feb 09 04:00:15 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149355116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 19.aon_timer_jump.1149355116
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.2642347857
Short name	T178
Test name
Test status
Simulation time	202660436999 ps
CPU time	106.92 seconds
Started	Feb 09 04:03:19 AM UTC 25
Finished	Feb 09 04:05:08 AM UTC 25
Peak memory	200732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642347857 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all.2642347857
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/28.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.3739913572
Short name	T155
Test name
Test status
Simulation time	438092048 ps
CPU time	2.26 seconds
Started	Feb 09 04:03:41 AM UTC 25
Finished	Feb 09 04:03:45 AM UTC 25
Peak memory	200604 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739913572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 29.aon_timer_jump.3739913572
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/29.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.668803811
Short name	T148
Test name
Test status
Simulation time	597180304 ps
CPU time	3.1 seconds
Started	Feb 09 04:04:23 AM UTC 25
Finished	Feb 09 04:04:27 AM UTC 25
Peak memory	200868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668803811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 33.aon_timer_jump.668803811
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/33.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.2703717475
Short name	T159
Test name
Test status
Simulation time	148616753806 ps
CPU time	94.81 seconds
Started	Feb 09 04:04:31 AM UTC 25
Finished	Feb 09 04:06:08 AM UTC 25
Peak memory	200996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703717475 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.2703717475
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/33.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.3893632803
Short name	T14
Test name
Test status
Simulation time	458133016 ps
CPU time	1.34 seconds
Started	Feb 09 03:55:02 AM UTC 25
Finished	Feb 09 03:55:04 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893632803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.aon_timer_jump.3893632803
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.3480333984
Short name	T122
Test name
Test status
Simulation time	598275106 ps
CPU time	1.32 seconds
Started	Feb 09 04:08:06 AM UTC 25
Finished	Feb 09 04:08:08 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480333984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 44.aon_timer_jump.3480333984
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/44.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all_with_rand_reset.298669183
Short name	T46
Test name
Test status
Simulation time	26616467211 ps
CPU time	259.47 seconds
Started	Feb 09 03:58:10 AM UTC 25
Finished	Feb 09 04:02:33 AM UTC 25
Peak memory	220868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298669183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_str ess_all_with_rand_reset.298669183
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.3312630800
Short name	T176
Test name
Test status
Simulation time	363969246 ps
CPU time	1.19 seconds
Started	Feb 09 03:58:45 AM UTC 25
Finished	Feb 09 03:58:47 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312630800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 15.aon_timer_jump.3312630800
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.3305865389
Short name	T115
Test name
Test status
Simulation time	258054842672 ps
CPU time	359.85 seconds
Started	Feb 09 04:00:10 AM UTC 25
Finished	Feb 09 04:06:14 AM UTC 25
Peak memory	200804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305865389 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.3305865389
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.255523904
Short name	T169
Test name
Test status
Simulation time	423918119 ps
CPU time	1.25 seconds
Started	Feb 09 04:00:23 AM UTC 25
Finished	Feb 09 04:00:26 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255523904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 20.aon_timer_jump.255523904
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/20.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.3348832509
Short name	T111
Test name
Test status
Simulation time	552385172 ps
CPU time	1 seconds
Started	Feb 09 04:00:33 AM UTC 25
Finished	Feb 09 04:00:35 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348832509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 21.aon_timer_jump.3348832509
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/21.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.3442615987
Short name	T106
Test name
Test status
Simulation time	374092031 ps
CPU time	1.36 seconds
Started	Feb 09 04:02:14 AM UTC 25
Finished	Feb 09 04:02:16 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442615987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 25.aon_timer_jump.3442615987
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/25.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.3170214371
Short name	T173
Test name
Test status
Simulation time	411900489 ps
CPU time	1.17 seconds
Started	Feb 09 04:05:35 AM UTC 25
Finished	Feb 09 04:05:37 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170214371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 36.aon_timer_jump.3170214371
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/36.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.2920967845
Short name	T89
Test name
Test status
Simulation time	363463282 ps
CPU time	2.06 seconds
Started	Feb 09 04:05:47 AM UTC 25
Finished	Feb 09 04:05:50 AM UTC 25
Peak memory	200680 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920967845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 38.aon_timer_jump.2920967845
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/38.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.1211453043
Short name	T174
Test name
Test status
Simulation time	175927581456 ps
CPU time	233.43 seconds
Started	Feb 09 03:56:58 AM UTC 25
Finished	Feb 09 04:00:55 AM UTC 25
Peak memory	201000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211453043 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.1211453043
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.903885279
Short name	T2
Test name
Test status
Simulation time	481042159 ps
CPU time	1.49 seconds
Started	Feb 09 03:54:36 AM UTC 25
Finished	Feb 09 03:54:38 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903885279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.aon_timer_jump.903885279
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all_with_rand_reset.963546179
Short name	T49
Test name
Test status
Simulation time	211905787710 ps
CPU time	545.36 seconds
Started	Feb 09 03:54:40 AM UTC 25
Finished	Feb 09 04:03:52 AM UTC 25
Peak memory	210992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963546179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stre ss_all_with_rand_reset.963546179
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all.3139226208
Short name	T104
Test name
Test status
Simulation time	271512790886 ps
CPU time	93.76 seconds
Started	Feb 09 04:00:36 AM UTC 25
Finished	Feb 09 04:02:12 AM UTC 25
Peak memory	200804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139226208 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all.3139226208
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/21.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.4242463871
Short name	T124
Test name
Test status
Simulation time	428947639 ps
CPU time	2.4 seconds
Started	Feb 09 04:01:06 AM UTC 25
Finished	Feb 09 04:01:10 AM UTC 25
Peak memory	200936 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242463871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 22.aon_timer_jump.4242463871
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/22.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.3323561386
Short name	T199
Test name
Test status
Simulation time	495298067 ps
CPU time	2.64 seconds
Started	Feb 09 04:03:15 AM UTC 25
Finished	Feb 09 04:03:18 AM UTC 25
Peak memory	200872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323561386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 28.aon_timer_jump.3323561386
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/28.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.3441258291
Short name	T10
Test name
Test status
Simulation time	590336911 ps
CPU time	1.91 seconds
Started	Feb 09 03:54:50 AM UTC 25
Finished	Feb 09 03:54:54 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441258291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.aon_timer_jump.3441258291
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.1444404599
Short name	T191
Test name
Test status
Simulation time	377557965 ps
CPU time	1.24 seconds
Started	Feb 09 04:05:59 AM UTC 25
Finished	Feb 09 04:06:01 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444404599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 39.aon_timer_jump.1444404599
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/39.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.1399406085
Short name	T160
Test name
Test status
Simulation time	475545437 ps
CPU time	1.31 seconds
Started	Feb 09 04:08:36 AM UTC 25
Finished	Feb 09 04:08:38 AM UTC 25
Peak memory	198748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399406085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 45.aon_timer_jump.1399406085
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/45.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.1275186959
Short name	T200
Test name
Test status
Simulation time	530792647 ps
CPU time	1.2 seconds
Started	Feb 09 04:10:09 AM UTC 25
Finished	Feb 09 04:10:12 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275186959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 49.aon_timer_jump.1275186959
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/49.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all_with_rand_reset.1983318717
Short name	T47
Test name
Test status
Simulation time	40889960623 ps
CPU time	223.71 seconds
Started	Feb 09 03:59:53 AM UTC 25
Finished	Feb 09 04:03:40 AM UTC 25
Peak memory	221576 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983318717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_st ress_all_with_rand_reset.1983318717
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all.4259959446
Short name	T121
Test name
Test status
Simulation time	182124116130 ps
CPU time	132.3 seconds
Started	Feb 09 04:01:37 AM UTC 25
Finished	Feb 09 04:03:51 AM UTC 25
Peak memory	200804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259959446 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all.4259959446
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/23.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.2746001937
Short name	T164
Test name
Test status
Simulation time	621772210 ps
CPU time	1.04 seconds
Started	Feb 09 04:07:33 AM UTC 25
Finished	Feb 09 04:07:35 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746001937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 43.aon_timer_jump.2746001937
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/43.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all_with_rand_reset.3018789756
Short name	T190
Test name
Test status
Simulation time	25922209849 ps
CPU time	187.04 seconds
Started	Feb 09 04:07:36 AM UTC 25
Finished	Feb 09 04:10:46 AM UTC 25
Peak memory	215404 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018789756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_st ress_all_with_rand_reset.3018789756
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.1643785946
Short name	T197
Test name
Test status
Simulation time	484667085 ps
CPU time	2.79 seconds
Started	Feb 09 04:08:45 AM UTC 25
Finished	Feb 09 04:08:49 AM UTC 25
Peak memory	200872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643785946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 46.aon_timer_jump.1643785946
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/46.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.1701388286
Short name	T198
Test name
Test status
Simulation time	481714071397 ps
CPU time	746.18 seconds
Started	Feb 09 04:08:49 AM UTC 25
Finished	Feb 09 04:21:22 AM UTC 25
Peak memory	200804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701388286 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.1701388286
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/46.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.1759394187
Short name	T154
Test name
Test status
Simulation time	465414685 ps
CPU time	2.43 seconds
Started	Feb 09 04:09:05 AM UTC 25
Finished	Feb 09 04:09:09 AM UTC 25
Peak memory	200604 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759394187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 47.aon_timer_jump.1759394187
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/47.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.2787943526
Short name	T185
Test name
Test status
Simulation time	588735498 ps
CPU time	3.01 seconds
Started	Feb 09 04:09:43 AM UTC 25
Finished	Feb 09 04:09:47 AM UTC 25
Peak memory	200872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787943526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 48.aon_timer_jump.2787943526
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/48.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.4134620638
Short name	T58
Test name
Test status
Simulation time	560553017 ps
CPU time	1.02 seconds
Started	Feb 09 03:55:18 AM UTC 25
Finished	Feb 09 03:55:20 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134620638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.aon_timer_jump.4134620638
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.1844528283
Short name	T25
Test name
Test status
Simulation time	541393538 ps
CPU time	2.73 seconds
Started	Feb 09 03:55:41 AM UTC 25
Finished	Feb 09 03:55:45 AM UTC 25
Peak memory	200872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844528283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 6.aon_timer_jump.1844528283
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.1337355907
Short name	T41
Test name
Test status
Simulation time	523873341 ps
CPU time	1.55 seconds
Started	Feb 09 03:55:53 AM UTC 25
Finished	Feb 09 03:55:55 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337355907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.aon_timer_jump.1337355907
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.4091482444
Short name	T194
Test name
Test status
Simulation time	423223761 ps
CPU time	0.93 seconds
Started	Feb 09 03:56:52 AM UTC 25
Finished	Feb 09 03:56:54 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091482444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 9.aon_timer_jump.4091482444
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1438291252
Short name	T40
Test name
Test status
Simulation time	8234540262 ps
CPU time	28.08 seconds
Started	Feb 09 04:10:31 AM UTC 25
Finished	Feb 09 04:11:00 AM UTC 25
Peak memory	206952 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438291252 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.1438291252
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.1406633443
Short name	T4
Test name
Test status
Simulation time	522885266 ps
CPU time	1.83 seconds
Started	Feb 09 03:54:40 AM UTC 25
Finished	Feb 09 03:54:43 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406633443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.aon_timer_jump.1406633443
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.211679733
Short name	T6
Test name
Test status
Simulation time	398501799 ps
CPU time	2.11 seconds
Started	Feb 09 03:54:42 AM UTC 25
Finished	Feb 09 03:54:46 AM UTC 25
Peak memory	200676 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211679733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.aon_timer_jump.211679733
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.3338985510
Short name	T85
Test name
Test status
Simulation time	398278580 ps
CPU time	1.11 seconds
Started	Feb 09 04:05:40 AM UTC 25
Finished	Feb 09 04:05:43 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338985510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 37.aon_timer_jump.3338985510
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/37.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.3803916678
Short name	T180
Test name
Test status
Simulation time	525493905 ps
CPU time	1.28 seconds
Started	Feb 09 04:06:13 AM UTC 25
Finished	Feb 09 04:06:15 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803916678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 40.aon_timer_jump.3803916678
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/40.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.3991897082
Short name	T184
Test name
Test status
Simulation time	503831948 ps
CPU time	2.27 seconds
Started	Feb 09 04:07:22 AM UTC 25
Finished	Feb 09 04:07:26 AM UTC 25
Peak memory	200616 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991897082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 42.aon_timer_jump.3991897082
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/42.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.687329516
Short name	T42
Test name
Test status
Simulation time	924618255 ps
CPU time	2.32 seconds
Started	Feb 09 04:10:23 AM UTC 25
Finished	Feb 09 04:10:26 AM UTC 25
Peak memory	201364 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687329516 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.687329516
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1015600818
Short name	T283
Test name
Test status
Simulation time	490985982 ps
CPU time	2.52 seconds
Started	Feb 09 04:10:29 AM UTC 25
Finished	Feb 09 04:10:33 AM UTC 25
Peak memory	205772 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015 600818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_ran d_reset.1015600818
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.1219967689
Short name	T43
Test name
Test status
Simulation time	393258309 ps
CPU time	1.53 seconds
Started	Feb 09 04:10:26 AM UTC 25
Finished	Feb 09 04:10:28 AM UTC 25
Peak memory	201992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219967689 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1219967689
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.3786802197
Short name	T279
Test name
Test status
Simulation time	373841421 ps
CPU time	0.96 seconds
Started	Feb 09 04:10:20 AM UTC 25
Finished	Feb 09 04:10:22 AM UTC 25
Peak memory	202428 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786802197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3786802197
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4036178753
Short name	T281
Test name
Test status
Simulation time	479396772 ps
CPU time	2.3 seconds
Started	Feb 09 04:10:23 AM UTC 25
Finished	Feb 09 04:10:26 AM UTC 25
Peak memory	201384 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036178753 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.4036178753
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.868756731
Short name	T280
Test name
Test status
Simulation time	448587159 ps
CPU time	1.59 seconds
Started	Feb 09 04:10:20 AM UTC 25
Finished	Feb 09 04:10:22 AM UTC 25
Peak memory	200452 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868756731 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.868756731
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.1722920962
Short name	T278
Test name
Test status
Simulation time	524252725 ps
CPU time	2.09 seconds
Started	Feb 09 04:10:12 AM UTC 25
Finished	Feb 09 04:10:16 AM UTC 25
Peak memory	207208 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722920962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1722920962
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3991060754
Short name	T63
Test name
Test status
Simulation time	649622259 ps
CPU time	1.85 seconds
Started	Feb 09 04:10:34 AM UTC 25
Finished	Feb 09 04:10:37 AM UTC 25
Peak memory	204548 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991060754 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_ timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.3991060754
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3242201177
Short name	T291
Test name
Test status
Simulation time	14017212959 ps
CPU time	9.87 seconds
Started	Feb 09 04:10:33 AM UTC 25
Finished	Feb 09 04:10:44 AM UTC 25
Peak memory	205784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242201177 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_ timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.3242201177
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3342833974
Short name	T64
Test name
Test status
Simulation time	948150690 ps
CPU time	3.62 seconds
Started	Feb 09 04:10:33 AM UTC 25
Finished	Feb 09 04:10:38 AM UTC 25
Peak memory	203396 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342833974 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_ timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.3342833974
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4071351597
Short name	T216
Test name
Test status
Simulation time	425378206 ps
CPU time	1.35 seconds
Started	Feb 09 04:10:35 AM UTC 25
Finished	Feb 09 04:10:38 AM UTC 25
Peak memory	204616 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071 351597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_ran d_reset.4071351597
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.3604773807
Short name	T62
Test name
Test status
Simulation time	499131195 ps
CPU time	2.23 seconds
Started	Feb 09 04:10:33 AM UTC 25
Finished	Feb 09 04:10:37 AM UTC 25
Peak memory	203528 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604773807 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3604773807
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.3253401222
Short name	T284
Test name
Test status
Simulation time	526538863 ps
CPU time	1.01 seconds
Started	Feb 09 04:10:31 AM UTC 25
Finished	Feb 09 04:10:33 AM UTC 25
Peak memory	200324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253401222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3253401222
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2051597395
Short name	T286
Test name
Test status
Simulation time	444088010 ps
CPU time	1.05 seconds
Started	Feb 09 04:10:32 AM UTC 25
Finished	Feb 09 04:10:34 AM UTC 25
Peak memory	200388 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051597395 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.2051597395
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3557002466
Short name	T285
Test name
Test status
Simulation time	296358849 ps
CPU time	1 seconds
Started	Feb 09 04:10:31 AM UTC 25
Finished	Feb 09 04:10:33 AM UTC 25
Peak memory	200448 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557002466 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_ timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.3557002466
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3583738273
Short name	T74
Test name
Test status
Simulation time	1047335593 ps
CPU time	1.97 seconds
Started	Feb 09 04:10:34 AM UTC 25
Finished	Feb 09 04:10:37 AM UTC 25
Peak memory	202500 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583738273 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.3583738273
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.2177322284
Short name	T282
Test name
Test status
Simulation time	494838434 ps
CPU time	2.15 seconds
Started	Feb 09 04:10:29 AM UTC 25
Finished	Feb 09 04:10:33 AM UTC 25
Peak memory	206968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177322284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2177322284
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.563837805
Short name	T333
Test name
Test status
Simulation time	475241932 ps
CPU time	1.31 seconds
Started	Feb 09 04:11:13 AM UTC 25
Finished	Feb 09 04:11:15 AM UTC 25
Peak memory	204552 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5638 37805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_ran d_reset.563837805
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.642359830
Short name	T70
Test name
Test status
Simulation time	450209766 ps
CPU time	1.64 seconds
Started	Feb 09 04:11:12 AM UTC 25
Finished	Feb 09 04:11:14 AM UTC 25
Peak memory	202412 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642359830 -assert nopostproc +UVM_TESTNAME=aon_timer_base _test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.642359830
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.484762432
Short name	T331
Test name
Test status
Simulation time	499756851 ps
CPU time	0.88 seconds
Started	Feb 09 04:11:12 AM UTC 25
Finished	Feb 09 04:11:14 AM UTC 25
Peak memory	200372 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484762432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.484762432
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3898696531
Short name	T337
Test name
Test status
Simulation time	2150528592 ps
CPU time	2.54 seconds
Started	Feb 09 04:11:13 AM UTC 25
Finished	Feb 09 04:11:16 AM UTC 25
Peak memory	205436 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898696531 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.3898696531
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.1981833119
Short name	T335
Test name
Test status
Simulation time	324196542 ps
CPU time	2.69 seconds
Started	Feb 09 04:11:11 AM UTC 25
Finished	Feb 09 04:11:15 AM UTC 25
Peak memory	207024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981833119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1981833119
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3983358947
Short name	T345
Test name
Test status
Simulation time	8663246846 ps
CPU time	7.66 seconds
Started	Feb 09 04:11:12 AM UTC 25
Finished	Feb 09 04:11:20 AM UTC 25
Peak memory	206956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983358947 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.3983358947
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2857980188
Short name	T341
Test name
Test status
Simulation time	477944095 ps
CPU time	1.49 seconds
Started	Feb 09 04:11:15 AM UTC 25
Finished	Feb 09 04:11:18 AM UTC 25
Peak memory	204496 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857 980188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_ra nd_reset.2857980188
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.4014059965
Short name	T340
Test name
Test status
Simulation time	414380683 ps
CPU time	2.54 seconds
Started	Feb 09 04:11:14 AM UTC 25
Finished	Feb 09 04:11:17 AM UTC 25
Peak memory	203520 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014059965 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.4014059965
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.1579306223
Short name	T332
Test name
Test status
Simulation time	390120224 ps
CPU time	0.98 seconds
Started	Feb 09 04:11:13 AM UTC 25
Finished	Feb 09 04:11:15 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579306223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1579306223
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1526910829
Short name	T347
Test name
Test status
Simulation time	2403877826 ps
CPU time	5.86 seconds
Started	Feb 09 04:11:14 AM UTC 25
Finished	Feb 09 04:11:21 AM UTC 25
Peak memory	203388 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526910829 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.1526910829
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.1226091200
Short name	T338
Test name
Test status
Simulation time	694873102 ps
CPU time	2.97 seconds
Started	Feb 09 04:11:13 AM UTC 25
Finished	Feb 09 04:11:17 AM UTC 25
Peak memory	207048 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226091200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1226091200
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2414738926
Short name	T201
Test name
Test status
Simulation time	4804175309 ps
CPU time	2.08 seconds
Started	Feb 09 04:11:13 AM UTC 25
Finished	Feb 09 04:11:16 AM UTC 25
Peak memory	205000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414738926 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.2414738926
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1412197769
Short name	T346
Test name
Test status
Simulation time	467690521 ps
CPU time	2.21 seconds
Started	Feb 09 04:11:17 AM UTC 25
Finished	Feb 09 04:11:21 AM UTC 25
Peak memory	205512 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412 197769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_ra nd_reset.1412197769
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.1263889322
Short name	T343
Test name
Test status
Simulation time	452897253 ps
CPU time	1.15 seconds
Started	Feb 09 04:11:16 AM UTC 25
Finished	Feb 09 04:11:18 AM UTC 25
Peak memory	202492 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263889322 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1263889322
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.153858300
Short name	T342
Test name
Test status
Simulation time	292164255 ps
CPU time	1.03 seconds
Started	Feb 09 04:11:16 AM UTC 25
Finished	Feb 09 04:11:18 AM UTC 25
Peak memory	200384 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153858300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.153858300
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3044070216
Short name	T353
Test name
Test status
Simulation time	2278380965 ps
CPU time	3.57 seconds
Started	Feb 09 04:11:17 AM UTC 25
Finished	Feb 09 04:11:22 AM UTC 25
Peak memory	205580 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044070216 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.3044070216
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.3543232915
Short name	T350
Test name
Test status
Simulation time	634331932 ps
CPU time	4.08 seconds
Started	Feb 09 04:11:16 AM UTC 25
Finished	Feb 09 04:11:21 AM UTC 25
Peak memory	206972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543232915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3543232915
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3229313728
Short name	T379
Test name
Test status
Simulation time	8418149355 ps
CPU time	13.82 seconds
Started	Feb 09 04:11:16 AM UTC 25
Finished	Feb 09 04:11:31 AM UTC 25
Peak memory	207272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229313728 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.3229313728
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2287440184
Short name	T355
Test name
Test status
Simulation time	285670529 ps
CPU time	1.8 seconds
Started	Feb 09 04:11:20 AM UTC 25
Finished	Feb 09 04:11:22 AM UTC 25
Peak memory	204316 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287 440184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_ra nd_reset.2287440184
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.924597723
Short name	T348
Test name
Test status
Simulation time	365676742 ps
CPU time	1.39 seconds
Started	Feb 09 04:11:18 AM UTC 25
Finished	Feb 09 04:11:21 AM UTC 25
Peak memory	200384 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924597723 -assert nopostproc +UVM_TESTNAME=aon_timer_base _test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.924597723
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.2423739338
Short name	T349
Test name
Test status
Simulation time	377903251 ps
CPU time	1.47 seconds
Started	Feb 09 04:11:18 AM UTC 25
Finished	Feb 09 04:11:21 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423739338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2423739338
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3570249101
Short name	T354
Test name
Test status
Simulation time	1446428644 ps
CPU time	2.02 seconds
Started	Feb 09 04:11:18 AM UTC 25
Finished	Feb 09 04:11:22 AM UTC 25
Peak memory	203528 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570249101 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.3570249101
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.2573252420
Short name	T351
Test name
Test status
Simulation time	789349673 ps
CPU time	2.85 seconds
Started	Feb 09 04:11:17 AM UTC 25
Finished	Feb 09 04:11:21 AM UTC 25
Peak memory	207060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573252420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2573252420
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2923952902
Short name	T352
Test name
Test status
Simulation time	4740974374 ps
CPU time	2.94 seconds
Started	Feb 09 04:11:17 AM UTC 25
Finished	Feb 09 04:11:21 AM UTC 25
Peak memory	206852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923952902 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.2923952902
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3004904003
Short name	T359
Test name
Test status
Simulation time	550666015 ps
CPU time	1.36 seconds
Started	Feb 09 04:11:22 AM UTC 25
Finished	Feb 09 04:11:25 AM UTC 25
Peak memory	205952 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004 904003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_ra nd_reset.3004904003
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.95862895
Short name	T358
Test name
Test status
Simulation time	543378308 ps
CPU time	1.19 seconds
Started	Feb 09 04:11:22 AM UTC 25
Finished	Feb 09 04:11:24 AM UTC 25
Peak memory	200444 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95862895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_ test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.95862895
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.3786508440
Short name	T356
Test name
Test status
Simulation time	398107945 ps
CPU time	0.77 seconds
Started	Feb 09 04:11:21 AM UTC 25
Finished	Feb 09 04:11:23 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786508440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3786508440
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.872717950
Short name	T366
Test name
Test status
Simulation time	1513950957 ps
CPU time	4.4 seconds
Started	Feb 09 04:11:22 AM UTC 25
Finished	Feb 09 04:11:28 AM UTC 25
Peak memory	203324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872717950 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.872717950
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.1154328943
Short name	T357
Test name
Test status
Simulation time	647607671 ps
CPU time	2.71 seconds
Started	Feb 09 04:11:20 AM UTC 25
Finished	Feb 09 04:11:23 AM UTC 25
Peak memory	206888 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154328943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1154328943
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.975883032
Short name	T363
Test name
Test status
Simulation time	7855107119 ps
CPU time	4.82 seconds
Started	Feb 09 04:11:21 AM UTC 25
Finished	Feb 09 04:11:27 AM UTC 25
Peak memory	207032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975883032 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ao n_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.975883032
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2126914723
Short name	T369
Test name
Test status
Simulation time	560915900 ps
CPU time	3.22 seconds
Started	Feb 09 04:11:23 AM UTC 25
Finished	Feb 09 04:11:28 AM UTC 25
Peak memory	206492 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126 914723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_ra nd_reset.2126914723
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.1483854194
Short name	T362
Test name
Test status
Simulation time	330335997 ps
CPU time	1.39 seconds
Started	Feb 09 04:11:23 AM UTC 25
Finished	Feb 09 04:11:26 AM UTC 25
Peak memory	202492 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483854194 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1483854194
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.2544961118
Short name	T360
Test name
Test status
Simulation time	379938800 ps
CPU time	1.51 seconds
Started	Feb 09 04:11:22 AM UTC 25
Finished	Feb 09 04:11:25 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544961118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2544961118
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3715627451
Short name	T375
Test name
Test status
Simulation time	1824699467 ps
CPU time	5.71 seconds
Started	Feb 09 04:11:23 AM UTC 25
Finished	Feb 09 04:11:30 AM UTC 25
Peak memory	203324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715627451 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.3715627451
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.3543142363
Short name	T365
Test name
Test status
Simulation time	378093488 ps
CPU time	3.62 seconds
Started	Feb 09 04:11:22 AM UTC 25
Finished	Feb 09 04:11:27 AM UTC 25
Peak memory	207176 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543142363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3543142363
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2661511578
Short name	T361
Test name
Test status
Simulation time	4381746846 ps
CPU time	2.34 seconds
Started	Feb 09 04:11:22 AM UTC 25
Finished	Feb 09 04:11:26 AM UTC 25
Peak memory	206564 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661511578 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.2661511578
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.870147585
Short name	T370
Test name
Test status
Simulation time	400385955 ps
CPU time	1.3 seconds
Started	Feb 09 04:11:25 AM UTC 25
Finished	Feb 09 04:11:28 AM UTC 25
Peak memory	204552 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8701 47585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_ran d_reset.870147585
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.1689663378
Short name	T367
Test name
Test status
Simulation time	539574724 ps
CPU time	1.87 seconds
Started	Feb 09 04:11:24 AM UTC 25
Finished	Feb 09 04:11:28 AM UTC 25
Peak memory	200436 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689663378 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1689663378
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.821485817
Short name	T368
Test name
Test status
Simulation time	424366565 ps
CPU time	2.23 seconds
Started	Feb 09 04:11:24 AM UTC 25
Finished	Feb 09 04:11:28 AM UTC 25
Peak memory	201336 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821485817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.821485817
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/16.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3601904120
Short name	T374
Test name
Test status
Simulation time	1107055703 ps
CPU time	4.36 seconds
Started	Feb 09 04:11:24 AM UTC 25
Finished	Feb 09 04:11:30 AM UTC 25
Peak memory	203596 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601904120 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.3601904120
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.4175385387
Short name	T364
Test name
Test status
Simulation time	557911595 ps
CPU time	2.25 seconds
Started	Feb 09 04:11:23 AM UTC 25
Finished	Feb 09 04:11:27 AM UTC 25
Peak memory	206976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175385387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4175385387
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3245578301
Short name	T372
Test name
Test status
Simulation time	4193553692 ps
CPU time	4.32 seconds
Started	Feb 09 04:11:23 AM UTC 25
Finished	Feb 09 04:11:29 AM UTC 25
Peak memory	206924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245578301 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.3245578301
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1114845044
Short name	T377
Test name
Test status
Simulation time	704020971 ps
CPU time	1.38 seconds
Started	Feb 09 04:11:28 AM UTC 25
Finished	Feb 09 04:11:30 AM UTC 25
Peak memory	206156 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114 845044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_ra nd_reset.1114845044
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.1503995023
Short name	T71
Test name
Test status
Simulation time	438124718 ps
CPU time	1.13 seconds
Started	Feb 09 04:11:27 AM UTC 25
Finished	Feb 09 04:11:29 AM UTC 25
Peak memory	202492 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503995023 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1503995023
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.2479135273
Short name	T371
Test name
Test status
Simulation time	548780520 ps
CPU time	0.87 seconds
Started	Feb 09 04:11:27 AM UTC 25
Finished	Feb 09 04:11:29 AM UTC 25
Peak memory	202436 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479135273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2479135273
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1630441948
Short name	T376
Test name
Test status
Simulation time	1274494077 ps
CPU time	1.26 seconds
Started	Feb 09 04:11:28 AM UTC 25
Finished	Feb 09 04:11:30 AM UTC 25
Peak memory	202496 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630441948 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.1630441948
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.2555811335
Short name	T373
Test name
Test status
Simulation time	542214361 ps
CPU time	2.99 seconds
Started	Feb 09 04:11:26 AM UTC 25
Finished	Feb 09 04:11:30 AM UTC 25
Peak memory	207216 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555811335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2555811335
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2907196871
Short name	T390
Test name
Test status
Simulation time	4548407296 ps
CPU time	7.11 seconds
Started	Feb 09 04:11:26 AM UTC 25
Finished	Feb 09 04:11:34 AM UTC 25
Peak memory	206316 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907196871 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.2907196871
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1238417618
Short name	T386
Test name
Test status
Simulation time	546583312 ps
CPU time	2.86 seconds
Started	Feb 09 04:11:29 AM UTC 25
Finished	Feb 09 04:11:33 AM UTC 25
Peak memory	205716 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238 417618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_ra nd_reset.1238417618
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.2235402177
Short name	T382
Test name
Test status
Simulation time	527098598 ps
CPU time	1.73 seconds
Started	Feb 09 04:11:29 AM UTC 25
Finished	Feb 09 04:11:32 AM UTC 25
Peak memory	202492 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235402177 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2235402177
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.2904848738
Short name	T380
Test name
Test status
Simulation time	282246145 ps
CPU time	1.37 seconds
Started	Feb 09 04:11:29 AM UTC 25
Finished	Feb 09 04:11:32 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904848738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2904848738
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3658165587
Short name	T381
Test name
Test status
Simulation time	1381737742 ps
CPU time	1.33 seconds
Started	Feb 09 04:11:29 AM UTC 25
Finished	Feb 09 04:11:32 AM UTC 25
Peak memory	202496 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658165587 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.3658165587
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.1966136206
Short name	T378
Test name
Test status
Simulation time	620395152 ps
CPU time	1.8 seconds
Started	Feb 09 04:11:28 AM UTC 25
Finished	Feb 09 04:11:31 AM UTC 25
Peak memory	205984 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966136206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1966136206
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2181679637
Short name	T394
Test name
Test status
Simulation time	8486503238 ps
CPU time	5.03 seconds
Started	Feb 09 04:11:29 AM UTC 25
Finished	Feb 09 04:11:35 AM UTC 25
Peak memory	207020 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181679637 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.2181679637
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1541437224
Short name	T389
Test name
Test status
Simulation time	296140114 ps
CPU time	1.44 seconds
Started	Feb 09 04:11:31 AM UTC 25
Finished	Feb 09 04:11:34 AM UTC 25
Peak memory	204480 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541 437224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_ra nd_reset.1541437224
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.123724845
Short name	T383
Test name
Test status
Simulation time	355985190 ps
CPU time	1.12 seconds
Started	Feb 09 04:11:30 AM UTC 25
Finished	Feb 09 04:11:32 AM UTC 25
Peak memory	200384 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123724845 -assert nopostproc +UVM_TESTNAME=aon_timer_base _test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.123724845
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.458223748
Short name	T384
Test name
Test status
Simulation time	470953267 ps
CPU time	1.74 seconds
Started	Feb 09 04:11:30 AM UTC 25
Finished	Feb 09 04:11:33 AM UTC 25
Peak memory	200388 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458223748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.458223748
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3361961189
Short name	T404
Test name
Test status
Simulation time	2124952652 ps
CPU time	5.81 seconds
Started	Feb 09 04:11:31 AM UTC 25
Finished	Feb 09 04:11:38 AM UTC 25
Peak memory	205380 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361961189 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.3361961189
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.1748819289
Short name	T385
Test name
Test status
Simulation time	502011385 ps
CPU time	2 seconds
Started	Feb 09 04:11:30 AM UTC 25
Finished	Feb 09 04:11:33 AM UTC 25
Peak memory	205984 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748819289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1748819289
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4024231966
Short name	T410
Test name
Test status
Simulation time	3921663242 ps
CPU time	7.47 seconds
Started	Feb 09 04:11:30 AM UTC 25
Finished	Feb 09 04:11:39 AM UTC 25
Peak memory	206860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024231966 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.4024231966
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.150249640
Short name	T65
Test name
Test status
Simulation time	527354605 ps
CPU time	1.92 seconds
Started	Feb 09 04:10:44 AM UTC 25
Finished	Feb 09 04:10:47 AM UTC 25
Peak memory	202496 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150249640 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.150249640
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4173885434
Short name	T344
Test name
Test status
Simulation time	13780591651 ps
CPU time	35.78 seconds
Started	Feb 09 04:10:43 AM UTC 25
Finished	Feb 09 04:11:20 AM UTC 25
Peak memory	205524 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173885434 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_ timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.4173885434
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.892496100
Short name	T66
Test name
Test status
Simulation time	915025537 ps
CPU time	4.1 seconds
Started	Feb 09 04:10:42 AM UTC 25
Finished	Feb 09 04:10:47 AM UTC 25
Peak memory	201416 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892496100 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.892496100
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3509790886
Short name	T293
Test name
Test status
Simulation time	390226464 ps
CPU time	2.25 seconds
Started	Feb 09 04:10:45 AM UTC 25
Finished	Feb 09 04:10:48 AM UTC 25
Peak memory	205440 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509 790886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_ran d_reset.3509790886
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.3980629416
Short name	T292
Test name
Test status
Simulation time	438728401 ps
CPU time	1.71 seconds
Started	Feb 09 04:10:43 AM UTC 25
Finished	Feb 09 04:10:46 AM UTC 25
Peak memory	202428 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980629416 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3980629416
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.2774088803
Short name	T288
Test name
Test status
Simulation time	505739443 ps
CPU time	1.86 seconds
Started	Feb 09 04:10:39 AM UTC 25
Finished	Feb 09 04:10:42 AM UTC 25
Peak memory	200384 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774088803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2774088803
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3823689404
Short name	T287
Test name
Test status
Simulation time	385457251 ps
CPU time	1.09 seconds
Started	Feb 09 04:10:39 AM UTC 25
Finished	Feb 09 04:10:41 AM UTC 25
Peak memory	200388 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823689404 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.3823689404
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.73370021
Short name	T289
Test name
Test status
Simulation time	360582361 ps
CPU time	2.01 seconds
Started	Feb 09 04:10:39 AM UTC 25
Finished	Feb 09 04:10:42 AM UTC 25
Peak memory	200444 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73370021 -assert nopostproc +UVM_TESTNAME=aon_timer _base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_ti mer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.73370021
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2541725742
Short name	T75
Test name
Test status
Simulation time	864293164 ps
CPU time	4.86 seconds
Started	Feb 09 04:10:45 AM UTC 25
Finished	Feb 09 04:10:51 AM UTC 25
Peak memory	203324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541725742 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.2541725742
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.2077534446
Short name	T290
Test name
Test status
Simulation time	567902538 ps
CPU time	4.89 seconds
Started	Feb 09 04:10:37 AM UTC 25
Finished	Feb 09 04:10:44 AM UTC 25
Peak memory	206984 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077534446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2077534446
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.952130636
Short name	T39
Test name
Test status
Simulation time	8811630739 ps
CPU time	13.41 seconds
Started	Feb 09 04:10:39 AM UTC 25
Finished	Feb 09 04:10:53 AM UTC 25
Peak memory	207080 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952130636 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ao n_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.952130636
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.2140265198
Short name	T391
Test name
Test status
Simulation time	427365251 ps
CPU time	1.62 seconds
Started	Feb 09 04:11:31 AM UTC 25
Finished	Feb 09 04:11:34 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140265198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2140265198
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/20.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.60995016
Short name	T388
Test name
Test status
Simulation time	427192844 ps
CPU time	1.12 seconds
Started	Feb 09 04:11:31 AM UTC 25
Finished	Feb 09 04:11:34 AM UTC 25
Peak memory	200364 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60995016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_tes t +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.60995016
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/21.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.3514654208
Short name	T387
Test name
Test status
Simulation time	476828529 ps
CPU time	0.95 seconds
Started	Feb 09 04:11:31 AM UTC 25
Finished	Feb 09 04:11:33 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514654208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3514654208
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/22.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.2567737481
Short name	T397
Test name
Test status
Simulation time	441289615 ps
CPU time	2.24 seconds
Started	Feb 09 04:11:33 AM UTC 25
Finished	Feb 09 04:11:36 AM UTC 25
Peak memory	201144 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567737481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2567737481
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/23.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.638260003
Short name	T393
Test name
Test status
Simulation time	411034480 ps
CPU time	1.5 seconds
Started	Feb 09 04:11:33 AM UTC 25
Finished	Feb 09 04:11:35 AM UTC 25
Peak memory	200236 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638260003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.638260003
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/24.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.3314529234
Short name	T392
Test name
Test status
Simulation time	458552465 ps
CPU time	1.01 seconds
Started	Feb 09 04:11:33 AM UTC 25
Finished	Feb 09 04:11:35 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314529234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3314529234
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/25.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.761081990
Short name	T395
Test name
Test status
Simulation time	310084240 ps
CPU time	1.76 seconds
Started	Feb 09 04:11:33 AM UTC 25
Finished	Feb 09 04:11:36 AM UTC 25
Peak memory	200388 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761081990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.761081990
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.1792315104
Short name	T399
Test name
Test status
Simulation time	480824159 ps
CPU time	1.67 seconds
Started	Feb 09 04:11:34 AM UTC 25
Finished	Feb 09 04:11:37 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792315104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1792315104
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.2573530522
Short name	T398
Test name
Test status
Simulation time	347749706 ps
CPU time	1.22 seconds
Started	Feb 09 04:11:34 AM UTC 25
Finished	Feb 09 04:11:36 AM UTC 25
Peak memory	202436 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573530522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2573530522
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/28.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.723008201
Short name	T402
Test name
Test status
Simulation time	430653282 ps
CPU time	1.85 seconds
Started	Feb 09 04:11:34 AM UTC 25
Finished	Feb 09 04:11:37 AM UTC 25
Peak memory	200388 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723008201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.723008201
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/29.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2008070776
Short name	T299
Test name
Test status
Simulation time	519743055 ps
CPU time	1.5 seconds
Started	Feb 09 04:10:51 AM UTC 25
Finished	Feb 09 04:10:54 AM UTC 25
Peak memory	202500 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008070776 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_ timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.2008070776
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1025176191
Short name	T68
Test name
Test status
Simulation time	7063103245 ps
CPU time	11.59 seconds
Started	Feb 09 04:10:50 AM UTC 25
Finished	Feb 09 04:11:03 AM UTC 25
Peak memory	205784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025176191 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_ timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.1025176191
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3236703797
Short name	T298
Test name
Test status
Simulation time	880875847 ps
CPU time	3.17 seconds
Started	Feb 09 04:10:49 AM UTC 25
Finished	Feb 09 04:10:53 AM UTC 25
Peak memory	201476 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236703797 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_ timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.3236703797
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1874631684
Short name	T300
Test name
Test status
Simulation time	448473421 ps
CPU time	2.23 seconds
Started	Feb 09 04:10:51 AM UTC 25
Finished	Feb 09 04:10:55 AM UTC 25
Peak memory	205708 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874 631684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_ran d_reset.1874631684
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.2762489832
Short name	T67
Test name
Test status
Simulation time	467002442 ps
CPU time	1.62 seconds
Started	Feb 09 04:10:50 AM UTC 25
Finished	Feb 09 04:10:53 AM UTC 25
Peak memory	202428 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762489832 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2762489832
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.3585629082
Short name	T296
Test name
Test status
Simulation time	487770278 ps
CPU time	1.52 seconds
Started	Feb 09 04:10:48 AM UTC 25
Finished	Feb 09 04:10:51 AM UTC 25
Peak memory	202428 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585629082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3585629082
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1195580827
Short name	T297
Test name
Test status
Simulation time	503936256 ps
CPU time	1.85 seconds
Started	Feb 09 04:10:49 AM UTC 25
Finished	Feb 09 04:10:52 AM UTC 25
Peak memory	200388 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195580827 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.1195580827
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.2340639433
Short name	T295
Test name
Test status
Simulation time	383095912 ps
CPU time	1.22 seconds
Started	Feb 09 04:10:48 AM UTC 25
Finished	Feb 09 04:10:50 AM UTC 25
Peak memory	200444 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340639433 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_ timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.2340639433
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3235880723
Short name	T76
Test name
Test status
Simulation time	2190175296 ps
CPU time	5.89 seconds
Started	Feb 09 04:10:51 AM UTC 25
Finished	Feb 09 04:10:58 AM UTC 25
Peak memory	205432 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235880723 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.3235880723
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.2902699209
Short name	T294
Test name
Test status
Simulation time	1006303202 ps
CPU time	2.36 seconds
Started	Feb 09 04:10:46 AM UTC 25
Finished	Feb 09 04:10:50 AM UTC 25
Peak memory	206968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902699209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2902699209
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1139770008
Short name	T202
Test name
Test status
Simulation time	8289480814 ps
CPU time	19.97 seconds
Started	Feb 09 04:10:47 AM UTC 25
Finished	Feb 09 04:11:08 AM UTC 25
Peak memory	207020 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139770008 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.1139770008
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.623734133
Short name	T396
Test name
Test status
Simulation time	540756579 ps
CPU time	0.82 seconds
Started	Feb 09 04:11:34 AM UTC 25
Finished	Feb 09 04:11:36 AM UTC 25
Peak memory	200388 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623734133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.623734133
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/30.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.3647116222
Short name	T400
Test name
Test status
Simulation time	562327684 ps
CPU time	0.81 seconds
Started	Feb 09 04:11:35 AM UTC 25
Finished	Feb 09 04:11:37 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647116222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3647116222
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/31.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.4163733853
Short name	T401
Test name
Test status
Simulation time	333072981 ps
CPU time	1.89 seconds
Started	Feb 09 04:11:35 AM UTC 25
Finished	Feb 09 04:11:38 AM UTC 25
Peak memory	200136 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163733853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.4163733853
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/32.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2696757295
Short name	T409
Test name
Test status
Simulation time	496680857 ps
CPU time	2.53 seconds
Started	Feb 09 04:11:35 AM UTC 25
Finished	Feb 09 04:11:39 AM UTC 25
Peak memory	203128 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696757295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2696757295
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/33.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.3782130707
Short name	T405
Test name
Test status
Simulation time	389992867 ps
CPU time	2.13 seconds
Started	Feb 09 04:11:35 AM UTC 25
Finished	Feb 09 04:11:38 AM UTC 25
Peak memory	203324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782130707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3782130707
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/34.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.1658299844
Short name	T403
Test name
Test status
Simulation time	291865867 ps
CPU time	1.05 seconds
Started	Feb 09 04:11:35 AM UTC 25
Finished	Feb 09 04:11:37 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658299844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1658299844
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/35.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3961349102
Short name	T408
Test name
Test status
Simulation time	350708080 ps
CPU time	1.45 seconds
Started	Feb 09 04:11:36 AM UTC 25
Finished	Feb 09 04:11:39 AM UTC 25
Peak memory	202436 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961349102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3961349102
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/36.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.456305230
Short name	T406
Test name
Test status
Simulation time	526586236 ps
CPU time	1.17 seconds
Started	Feb 09 04:11:36 AM UTC 25
Finished	Feb 09 04:11:38 AM UTC 25
Peak memory	200388 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456305230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.456305230
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/37.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.213679655
Short name	T413
Test name
Test status
Simulation time	461871282 ps
CPU time	2.38 seconds
Started	Feb 09 04:11:36 AM UTC 25
Finished	Feb 09 04:11:40 AM UTC 25
Peak memory	201272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213679655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.213679655
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/38.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.71288917
Short name	T411
Test name
Test status
Simulation time	379196636 ps
CPU time	1.45 seconds
Started	Feb 09 04:11:36 AM UTC 25
Finished	Feb 09 04:11:39 AM UTC 25
Peak memory	202428 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71288917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_tes t +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.71288917
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/39.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3112230603
Short name	T306
Test name
Test status
Simulation time	563954326 ps
CPU time	1.54 seconds
Started	Feb 09 04:10:56 AM UTC 25
Finished	Feb 09 04:10:58 AM UTC 25
Peak memory	202400 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112230603 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_ timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.3112230603
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3439676881
Short name	T72
Test name
Test status
Simulation time	12380037798 ps
CPU time	69.67 seconds
Started	Feb 09 04:10:56 AM UTC 25
Finished	Feb 09 04:12:07 AM UTC 25
Peak memory	205652 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439676881 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_ timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.3439676881
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1924978894
Short name	T307
Test name
Test status
Simulation time	672839209 ps
CPU time	3.34 seconds
Started	Feb 09 04:10:55 AM UTC 25
Finished	Feb 09 04:10:59 AM UTC 25
Peak memory	201412 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924978894 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_ timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.1924978894
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2388168094
Short name	T310
Test name
Test status
Simulation time	396887139 ps
CPU time	2.14 seconds
Started	Feb 09 04:10:58 AM UTC 25
Finished	Feb 09 04:11:01 AM UTC 25
Peak memory	205948 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388 168094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_ran d_reset.2388168094
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.3123474458
Short name	T304
Test name
Test status
Simulation time	333428349 ps
CPU time	1.12 seconds
Started	Feb 09 04:10:55 AM UTC 25
Finished	Feb 09 04:10:57 AM UTC 25
Peak memory	202428 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123474458 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3123474458
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.2412922933
Short name	T301
Test name
Test status
Simulation time	300941260 ps
CPU time	1.83 seconds
Started	Feb 09 04:10:53 AM UTC 25
Finished	Feb 09 04:10:56 AM UTC 25
Peak memory	200384 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412922933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2412922933
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1926315242
Short name	T305
Test name
Test status
Simulation time	498753408 ps
CPU time	2.46 seconds
Started	Feb 09 04:10:54 AM UTC 25
Finished	Feb 09 04:10:57 AM UTC 25
Peak memory	201440 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926315242 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.1926315242
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.504052748
Short name	T302
Test name
Test status
Simulation time	458949256 ps
CPU time	1.04 seconds
Started	Feb 09 04:10:54 AM UTC 25
Finished	Feb 09 04:10:56 AM UTC 25
Peak memory	200444 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504052748 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.504052748
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1413996934
Short name	T78
Test name
Test status
Simulation time	1160590983 ps
CPU time	3.85 seconds
Started	Feb 09 04:10:57 AM UTC 25
Finished	Feb 09 04:11:02 AM UTC 25
Peak memory	203524 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413996934 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.1413996934
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.4234607672
Short name	T303
Test name
Test status
Simulation time	479304185 ps
CPU time	4.18 seconds
Started	Feb 09 04:10:52 AM UTC 25
Finished	Feb 09 04:10:57 AM UTC 25
Peak memory	206968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234607672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.4234607672
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.191076457
Short name	T318
Test name
Test status
Simulation time	8284563971 ps
CPU time	12.88 seconds
Started	Feb 09 04:10:53 AM UTC 25
Finished	Feb 09 04:11:07 AM UTC 25
Peak memory	207072 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191076457 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ao n_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.191076457
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.2008023161
Short name	T407
Test name
Test status
Simulation time	405457761 ps
CPU time	1.01 seconds
Started	Feb 09 04:11:36 AM UTC 25
Finished	Feb 09 04:11:38 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008023161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2008023161
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/40.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.594421454
Short name	T415
Test name
Test status
Simulation time	335848827 ps
CPU time	1.31 seconds
Started	Feb 09 04:11:37 AM UTC 25
Finished	Feb 09 04:11:40 AM UTC 25
Peak memory	200380 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594421454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.594421454
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/41.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.3129051648
Short name	T412
Test name
Test status
Simulation time	392130497 ps
CPU time	0.75 seconds
Started	Feb 09 04:11:37 AM UTC 25
Finished	Feb 09 04:11:39 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129051648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3129051648
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/42.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.4083240310
Short name	T416
Test name
Test status
Simulation time	353402039 ps
CPU time	1.39 seconds
Started	Feb 09 04:11:37 AM UTC 25
Finished	Feb 09 04:11:40 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083240310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.4083240310
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/43.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.1492600675
Short name	T414
Test name
Test status
Simulation time	451469553 ps
CPU time	0.89 seconds
Started	Feb 09 04:11:37 AM UTC 25
Finished	Feb 09 04:11:40 AM UTC 25
Peak memory	202436 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492600675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1492600675
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/44.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.927612748
Short name	T417
Test name
Test status
Simulation time	465384967 ps
CPU time	1.23 seconds
Started	Feb 09 04:11:38 AM UTC 25
Finished	Feb 09 04:11:40 AM UTC 25
Peak memory	200388 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927612748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.927612748
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/45.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.3828278891
Short name	T418
Test name
Test status
Simulation time	408047464 ps
CPU time	0.86 seconds
Started	Feb 09 04:11:39 AM UTC 25
Finished	Feb 09 04:11:41 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828278891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3828278891
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/46.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.1785389600
Short name	T420
Test name
Test status
Simulation time	356360794 ps
CPU time	1.35 seconds
Started	Feb 09 04:11:39 AM UTC 25
Finished	Feb 09 04:11:41 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785389600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1785389600
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/47.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.1632222112
Short name	T421
Test name
Test status
Simulation time	488403646 ps
CPU time	1.68 seconds
Started	Feb 09 04:11:39 AM UTC 25
Finished	Feb 09 04:11:42 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632222112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1632222112
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/48.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.2607929949
Short name	T419
Test name
Test status
Simulation time	390702128 ps
CPU time	1.03 seconds
Started	Feb 09 04:11:39 AM UTC 25
Finished	Feb 09 04:11:41 AM UTC 25
Peak memory	200392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607929949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2607929949
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/49.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1809320776
Short name	T311
Test name
Test status
Simulation time	514612672 ps
CPU time	1.66 seconds
Started	Feb 09 04:10:59 AM UTC 25
Finished	Feb 09 04:11:02 AM UTC 25
Peak memory	204616 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809 320776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_ran d_reset.1809320776
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.2448313282
Short name	T77
Test name
Test status
Simulation time	384836015 ps
CPU time	2.41 seconds
Started	Feb 09 04:10:58 AM UTC 25
Finished	Feb 09 04:11:02 AM UTC 25
Peak memory	203392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448313282 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2448313282
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.1691283485
Short name	T308
Test name
Test status
Simulation time	542780634 ps
CPU time	1.08 seconds
Started	Feb 09 04:10:58 AM UTC 25
Finished	Feb 09 04:11:00 AM UTC 25
Peak memory	202428 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691283485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1691283485
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2822669630
Short name	T80
Test name
Test status
Simulation time	2263343285 ps
CPU time	6.11 seconds
Started	Feb 09 04:10:59 AM UTC 25
Finished	Feb 09 04:11:07 AM UTC 25
Peak memory	203588 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822669630 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.2822669630
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.729720526
Short name	T309
Test name
Test status
Simulation time	463689414 ps
CPU time	1.79 seconds
Started	Feb 09 04:10:58 AM UTC 25
Finished	Feb 09 04:11:01 AM UTC 25
Peak memory	205972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729720526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.729720526
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3518997735
Short name	T328
Test name
Test status
Simulation time	4689488975 ps
CPU time	13.06 seconds
Started	Feb 09 04:10:58 AM UTC 25
Finished	Feb 09 04:11:12 AM UTC 25
Peak memory	205652 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518997735 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.3518997735
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1769662577
Short name	T315
Test name
Test status
Simulation time	454997128 ps
CPU time	1.83 seconds
Started	Feb 09 04:11:03 AM UTC 25
Finished	Feb 09 04:11:06 AM UTC 25
Peak memory	206048 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769 662577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_ran d_reset.1769662577
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.3700824189
Short name	T312
Test name
Test status
Simulation time	349162201 ps
CPU time	0.93 seconds
Started	Feb 09 04:11:01 AM UTC 25
Finished	Feb 09 04:11:03 AM UTC 25
Peak memory	200380 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700824189 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3700824189
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.358659527
Short name	T313
Test name
Test status
Simulation time	471022117 ps
CPU time	1.02 seconds
Started	Feb 09 04:11:01 AM UTC 25
Finished	Feb 09 04:11:03 AM UTC 25
Peak memory	200376 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358659527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.358659527
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2542408678
Short name	T79
Test name
Test status
Simulation time	1413778874 ps
CPU time	2.65 seconds
Started	Feb 09 04:11:03 AM UTC 25
Finished	Feb 09 04:11:06 AM UTC 25
Peak memory	203128 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542408678 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.2542408678
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.906034472
Short name	T314
Test name
Test status
Simulation time	483175962 ps
CPU time	3.53 seconds
Started	Feb 09 04:11:00 AM UTC 25
Finished	Feb 09 04:11:05 AM UTC 25
Peak memory	207212 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906034472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.906034472
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3927486307
Short name	T322
Test name
Test status
Simulation time	8422724615 ps
CPU time	7.42 seconds
Started	Feb 09 04:11:01 AM UTC 25
Finished	Feb 09 04:11:10 AM UTC 25
Peak memory	207204 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927486307 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/a on_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.3927486307
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4132076401
Short name	T320
Test name
Test status
Simulation time	360833994 ps
CPU time	1.99 seconds
Started	Feb 09 04:11:06 AM UTC 25
Finished	Feb 09 04:11:09 AM UTC 25
Peak memory	204616 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132 076401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_ran d_reset.4132076401
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.2679572786
Short name	T73
Test name
Test status
Simulation time	403230727 ps
CPU time	1.96 seconds
Started	Feb 09 04:11:05 AM UTC 25
Finished	Feb 09 04:11:08 AM UTC 25
Peak memory	202496 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679572786 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2679572786
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.270101483
Short name	T316
Test name
Test status
Simulation time	326658378 ps
CPU time	1.37 seconds
Started	Feb 09 04:11:04 AM UTC 25
Finished	Feb 09 04:11:06 AM UTC 25
Peak memory	200380 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270101483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_te st +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.270101483
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3109343229
Short name	T81
Test name
Test status
Simulation time	2448099476 ps
CPU time	2.49 seconds
Started	Feb 09 04:11:05 AM UTC 25
Finished	Feb 09 04:11:08 AM UTC 25
Peak memory	205636 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109343229 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.3109343229
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.4171714335
Short name	T319
Test name
Test status
Simulation time	528470186 ps
CPU time	3.16 seconds
Started	Feb 09 04:11:03 AM UTC 25
Finished	Feb 09 04:11:07 AM UTC 25
Peak memory	206908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171714335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.4171714335
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.658327537
Short name	T317
Test name
Test status
Simulation time	8714928579 ps
CPU time	8.07 seconds
Started	Feb 09 04:11:03 AM UTC 25
Finished	Feb 09 04:11:12 AM UTC 25
Peak memory	207020 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658327537 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ao n_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.658327537
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3279768645
Short name	T325
Test name
Test status
Simulation time	416798582 ps
CPU time	1.79 seconds
Started	Feb 09 04:11:08 AM UTC 25
Finished	Feb 09 04:11:11 AM UTC 25
Peak memory	204616 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279 768645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_ran d_reset.3279768645
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.3809548632
Short name	T69
Test name
Test status
Simulation time	502767778 ps
CPU time	2.46 seconds
Started	Feb 09 04:11:07 AM UTC 25
Finished	Feb 09 04:11:11 AM UTC 25
Peak memory	203456 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809548632 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3809548632
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.2564946095
Short name	T323
Test name
Test status
Simulation time	373935572 ps
CPU time	2.1 seconds
Started	Feb 09 04:11:07 AM UTC 25
Finished	Feb 09 04:11:10 AM UTC 25
Peak memory	201196 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564946095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2564946095
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3524545424
Short name	T324
Test name
Test status
Simulation time	1067594966 ps
CPU time	2.6 seconds
Started	Feb 09 04:11:07 AM UTC 25
Finished	Feb 09 04:11:11 AM UTC 25
Peak memory	203524 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524545424 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.3524545424
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.1482380214
Short name	T321
Test name
Test status
Simulation time	1020928569 ps
CPU time	2.94 seconds
Started	Feb 09 04:11:06 AM UTC 25
Finished	Feb 09 04:11:10 AM UTC 25
Peak memory	206968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482380214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1482380214
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.126242846
Short name	T339
Test name
Test status
Simulation time	4465378633 ps
CPU time	8.93 seconds
Started	Feb 09 04:11:07 AM UTC 25
Finished	Feb 09 04:11:17 AM UTC 25
Peak memory	207032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126242846 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ao n_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.126242846
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2956509566
Short name	T330
Test name
Test status
Simulation time	509040703 ps
CPU time	1.55 seconds
Started	Feb 09 04:11:10 AM UTC 25
Finished	Feb 09 04:11:13 AM UTC 25
Peak memory	206156 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956 509566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_ran d_reset.2956509566
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.3788157371
Short name	T329
Test name
Test status
Simulation time	527635261 ps
CPU time	0.96 seconds
Started	Feb 09 04:11:10 AM UTC 25
Finished	Feb 09 04:11:12 AM UTC 25
Peak memory	200380 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788157371 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3788157371
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.3560588927
Short name	T326
Test name
Test status
Simulation time	393604404 ps
CPU time	0.84 seconds
Started	Feb 09 04:11:09 AM UTC 25
Finished	Feb 09 04:11:11 AM UTC 25
Peak memory	200384 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560588927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3560588927
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3845545318
Short name	T336
Test name
Test status
Simulation time	1426201921 ps
CPU time	4.45 seconds
Started	Feb 09 04:11:10 AM UTC 25
Finished	Feb 09 04:11:16 AM UTC 25
Peak memory	203332 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845545318 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.3845545318
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.2312812196
Short name	T327
Test name
Test status
Simulation time	593914874 ps
CPU time	1.59 seconds
Started	Feb 09 04:11:09 AM UTC 25
Finished	Feb 09 04:11:12 AM UTC 25
Peak memory	205976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312812196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_t est +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2312812196
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.450236187
Short name	T334
Test name
Test status
Simulation time	8089391261 ps
CPU time	4.87 seconds
Started	Feb 09 04:11:09 AM UTC 25
Finished	Feb 09 04:11:15 AM UTC 25
Peak memory	207004 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450236187 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ao n_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.450236187
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.1356868245
Short name	T15
Test name
Test status
Simulation time	22914296870 ps
CPU time	32.49 seconds
Started	Feb 09 03:54:36 AM UTC 25
Finished	Feb 09 03:55:10 AM UTC 25
Peak memory	200732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356868245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1356868245
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.1785938220
Short name	T1
Test name
Test status
Simulation time	451799529 ps
CPU time	1.61 seconds
Started	Feb 09 03:54:36 AM UTC 25
Finished	Feb 09 03:54:38 AM UTC 25
Peak memory	200096 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785938220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1785938220
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all_with_rand_reset.2711847224
Short name	T23
Test name
Test status
Simulation time	77691414650 ps
CPU time	383.19 seconds
Started	Feb 09 03:54:37 AM UTC 25
Finished	Feb 09 04:01:05 AM UTC 25
Peak memory	217544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_tim er_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711847224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_str ess_all_with_rand_reset.2711847224
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.1631800854
Short name	T12
Test name
Test status
Simulation time	18454589670 ps
CPU time	13.59 seconds
Started	Feb 09 03:54:39 AM UTC 25
Finished	Feb 09 03:54:54 AM UTC 25
Peak memory	200996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631800854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1631800854
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.2745582849
Short name	T24
Test name
Test status
Simulation time	8370044947 ps
CPU time	23.48 seconds
Started	Feb 09 03:54:40 AM UTC 25
Finished	Feb 09 03:55:05 AM UTC 25
Peak memory	231764 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745582849 -assert nopostproc +UVM_TESTNAME=aon_timer_ba se_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2745582849
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.8826909
Short name	T3
Test name
Test status
Simulation time	589454904 ps
CPU time	1.08 seconds
Started	Feb 09 03:54:39 AM UTC 25
Finished	Feb 09 03:54:41 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8826909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ti mer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.8826909
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.3335523500
Short name	T189
Test name
Test status
Simulation time	588853354 ps
CPU time	1.15 seconds
Started	Feb 09 03:57:22 AM UTC 25
Finished	Feb 09 03:57:25 AM UTC 25
Peak memory	199548 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335523500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 10.aon_timer_jump.3335523500
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.3836064023
Short name	T54
Test name
Test status
Simulation time	23188936412 ps
CPU time	56.71 seconds
Started	Feb 09 03:57:18 AM UTC 25
Finished	Feb 09 03:58:17 AM UTC 25
Peak memory	200812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836064023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3836064023
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.3800807994
Short name	T30
Test name
Test status
Simulation time	510423995 ps
CPU time	2.49 seconds
Started	Feb 09 03:57:14 AM UTC 25
Finished	Feb 09 03:57:18 AM UTC 25
Peak memory	200876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800807994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3800807994
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.318622245
Short name	T32
Test name
Test status
Simulation time	493243063 ps
CPU time	1.11 seconds
Started	Feb 09 03:57:47 AM UTC 25
Finished	Feb 09 03:57:49 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318622245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 11.aon_timer_jump.318622245
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.2376812418
Short name	T52
Test name
Test status
Simulation time	26680419167 ps
CPU time	23.4 seconds
Started	Feb 09 03:57:47 AM UTC 25
Finished	Feb 09 03:58:11 AM UTC 25
Peak memory	200812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376812418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2376812418
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.265455268
Short name	T221
Test name
Test status
Simulation time	592077047 ps
CPU time	2.21 seconds
Started	Feb 09 03:57:43 AM UTC 25
Finished	Feb 09 03:57:46 AM UTC 25
Peak memory	200880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265455268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 11.aon_timer_smoke.265455268
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.2849743211
Short name	T210
Test name
Test status
Simulation time	24128432016 ps
CPU time	86.1 seconds
Started	Feb 09 03:57:57 AM UTC 25
Finished	Feb 09 03:59:26 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849743211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2849743211
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.911333998
Short name	T217
Test name
Test status
Simulation time	561169974 ps
CPU time	1.28 seconds
Started	Feb 09 03:57:53 AM UTC 25
Finished	Feb 09 03:57:56 AM UTC 25
Peak memory	199548 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911333998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 12.aon_timer_smoke.911333998
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.3168648032
Short name	T56
Test name
Test status
Simulation time	25940822746 ps
CPU time	11.34 seconds
Started	Feb 09 03:58:17 AM UTC 25
Finished	Feb 09 03:58:29 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168648032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3168648032
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.429749736
Short name	T53
Test name
Test status
Simulation time	383657598 ps
CPU time	2.23 seconds
Started	Feb 09 03:58:13 AM UTC 25
Finished	Feb 09 03:58:16 AM UTC 25
Peak memory	200612 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429749736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 13.aon_timer_smoke.429749736
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.3654971045
Short name	T213
Test name
Test status
Simulation time	51058966662 ps
CPU time	110.47 seconds
Started	Feb 09 03:58:31 AM UTC 25
Finished	Feb 09 04:00:24 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654971045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3654971045
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.2436005376
Short name	T57
Test name
Test status
Simulation time	513384511 ps
CPU time	1.24 seconds
Started	Feb 09 03:58:30 AM UTC 25
Finished	Feb 09 03:58:32 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436005376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2436005376
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.2214229607
Short name	T212
Test name
Test status
Simulation time	31285739836 ps
CPU time	93.15 seconds
Started	Feb 09 03:58:42 AM UTC 25
Finished	Feb 09 04:00:18 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214229607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2214229607
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.363702722
Short name	T222
Test name
Test status
Simulation time	529457129 ps
CPU time	1.49 seconds
Started	Feb 09 03:58:39 AM UTC 25
Finished	Feb 09 03:58:42 AM UTC 25
Peak memory	199548 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363702722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 15.aon_timer_smoke.363702722
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.4123602237
Short name	T207
Test name
Test status
Simulation time	18279492729 ps
CPU time	64.63 seconds
Started	Feb 09 03:58:57 AM UTC 25
Finished	Feb 09 04:00:03 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123602237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.4123602237
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/16.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.3816842840
Short name	T223
Test name
Test status
Simulation time	539136903 ps
CPU time	1.72 seconds
Started	Feb 09 03:58:56 AM UTC 25
Finished	Feb 09 03:58:59 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816842840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3816842840
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/16.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.3208837702
Short name	T225
Test name
Test status
Simulation time	6028547153 ps
CPU time	6.16 seconds
Started	Feb 09 03:59:17 AM UTC 25
Finished	Feb 09 03:59:25 AM UTC 25
Peak memory	200748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208837702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3208837702
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.1068951681
Short name	T224
Test name
Test status
Simulation time	588660211 ps
CPU time	1.68 seconds
Started	Feb 09 03:59:14 AM UTC 25
Finished	Feb 09 03:59:17 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068951681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1068951681
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.1014835334
Short name	T227
Test name
Test status
Simulation time	24068026781 ps
CPU time	21.65 seconds
Started	Feb 09 03:59:38 AM UTC 25
Finished	Feb 09 04:00:02 AM UTC 25
Peak memory	201068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014835334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1014835334
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.3662670329
Short name	T226
Test name
Test status
Simulation time	570479282 ps
CPU time	1.85 seconds
Started	Feb 09 03:59:34 AM UTC 25
Finished	Feb 09 03:59:37 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662670329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3662670329
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.4068125042
Short name	T205
Test name
Test status
Simulation time	13145869718 ps
CPU time	11.51 seconds
Started	Feb 09 04:00:10 AM UTC 25
Finished	Feb 09 04:00:23 AM UTC 25
Peak memory	201004 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068125042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.4068125042
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.3908462960
Short name	T228
Test name
Test status
Simulation time	462998034 ps
CPU time	2.29 seconds
Started	Feb 09 04:00:10 AM UTC 25
Finished	Feb 09 04:00:13 AM UTC 25
Peak memory	200608 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908462960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3908462960
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.1157466996
Short name	T20
Test name
Test status
Simulation time	4464260601 ps
CPU time	12.67 seconds
Started	Feb 09 03:54:46 AM UTC 25
Finished	Feb 09 03:55:01 AM UTC 25
Peak memory	231708 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157466996 -assert nopostproc +UVM_TESTNAME=aon_timer_ba se_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1157466996
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.1361683527
Short name	T5
Test name
Test status
Simulation time	494645410 ps
CPU time	1.26 seconds
Started	Feb 09 03:54:41 AM UTC 25
Finished	Feb 09 03:54:44 AM UTC 25
Peak memory	199304 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361683527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1361683527
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.1673286186
Short name	T211
Test name
Test status
Simulation time	27558032930 ps
CPU time	9.79 seconds
Started	Feb 09 04:00:22 AM UTC 25
Finished	Feb 09 04:00:33 AM UTC 25
Peak memory	201004 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673286186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1673286186
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/20.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.1050774847
Short name	T229
Test name
Test status
Simulation time	381728090 ps
CPU time	1.23 seconds
Started	Feb 09 04:00:19 AM UTC 25
Finished	Feb 09 04:00:21 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050774847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1050774847
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/20.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.1788241431
Short name	T232
Test name
Test status
Simulation time	13563536976 ps
CPU time	31.15 seconds
Started	Feb 09 04:00:33 AM UTC 25
Finished	Feb 09 04:01:05 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788241431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1788241431
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/21.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.4087953444
Short name	T230
Test name
Test status
Simulation time	485371740 ps
CPU time	1.9 seconds
Started	Feb 09 04:00:29 AM UTC 25
Finished	Feb 09 04:00:32 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087953444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.4087953444
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/21.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.3768041326
Short name	T233
Test name
Test status
Simulation time	22627803715 ps
CPU time	10.47 seconds
Started	Feb 09 04:00:59 AM UTC 25
Finished	Feb 09 04:01:11 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768041326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3768041326
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/22.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.3033847467
Short name	T231
Test name
Test status
Simulation time	585004264 ps
CPU time	1.02 seconds
Started	Feb 09 04:00:56 AM UTC 25
Finished	Feb 09 04:00:58 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033847467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3033847467
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/22.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.1949320955
Short name	T203
Test name
Test status
Simulation time	3605661688 ps
CPU time	2.94 seconds
Started	Feb 09 04:01:15 AM UTC 25
Finished	Feb 09 04:01:19 AM UTC 25
Peak memory	200676 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949320955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1949320955
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/23.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.1417240181
Short name	T234
Test name
Test status
Simulation time	514411086 ps
CPU time	2.48 seconds
Started	Feb 09 04:01:11 AM UTC 25
Finished	Feb 09 04:01:15 AM UTC 25
Peak memory	200876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417240181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1417240181
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/23.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.3830515130
Short name	T209
Test name
Test status
Simulation time	19895296149 ps
CPU time	66.37 seconds
Started	Feb 09 04:01:44 AM UTC 25
Finished	Feb 09 04:02:52 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830515130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3830515130
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/24.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.4020305692
Short name	T235
Test name
Test status
Simulation time	569573898 ps
CPU time	1.71 seconds
Started	Feb 09 04:01:40 AM UTC 25
Finished	Feb 09 04:01:42 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020305692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.4020305692
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/24.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.518456721
Short name	T108
Test name
Test status
Simulation time	6596198408 ps
CPU time	23.35 seconds
Started	Feb 09 04:02:13 AM UTC 25
Finished	Feb 09 04:02:38 AM UTC 25
Peak memory	200808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518456721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.518456721
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/25.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.112023743
Short name	T105
Test name
Test status
Simulation time	497206740 ps
CPU time	2.41 seconds
Started	Feb 09 04:02:10 AM UTC 25
Finished	Feb 09 04:02:13 AM UTC 25
Peak memory	200612 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112023743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 25.aon_timer_smoke.112023743
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/25.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.2124890680
Short name	T109
Test name
Test status
Simulation time	564494761 ps
CPU time	0.95 seconds
Started	Feb 09 04:02:38 AM UTC 25
Finished	Feb 09 04:02:40 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124890680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 26.aon_timer_jump.2124890680
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.2340517217
Short name	T206
Test name
Test status
Simulation time	10944015093 ps
CPU time	9.16 seconds
Started	Feb 09 04:02:36 AM UTC 25
Finished	Feb 09 04:02:47 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340517217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2340517217
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.1945936552
Short name	T107
Test name
Test status
Simulation time	351831502 ps
CPU time	1.39 seconds
Started	Feb 09 04:02:33 AM UTC 25
Finished	Feb 09 04:02:36 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945936552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1945936552
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.3038761520
Short name	T238
Test name
Test status
Simulation time	13959923572 ps
CPU time	17.53 seconds
Started	Feb 09 04:02:57 AM UTC 25
Finished	Feb 09 04:03:15 AM UTC 25
Peak memory	200812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038761520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3038761520
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.2757000465
Short name	T236
Test name
Test status
Simulation time	419820807 ps
CPU time	2.18 seconds
Started	Feb 09 04:02:53 AM UTC 25
Finished	Feb 09 04:02:56 AM UTC 25
Peak memory	200608 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757000465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2757000465
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.34789269
Short name	T86
Test name
Test status
Simulation time	57644317575 ps
CPU time	147.97 seconds
Started	Feb 09 04:03:14 AM UTC 25
Finished	Feb 09 04:05:44 AM UTC 25
Peak memory	201000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34789269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_t imer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.34789269
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/28.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.4225256004
Short name	T237
Test name
Test status
Simulation time	402159558 ps
CPU time	1.12 seconds
Started	Feb 09 04:03:11 AM UTC 25
Finished	Feb 09 04:03:13 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225256004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.4225256004
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/28.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.1868709303
Short name	T248
Test name
Test status
Simulation time	38022440447 ps
CPU time	88.43 seconds
Started	Feb 09 04:03:30 AM UTC 25
Finished	Feb 09 04:05:00 AM UTC 25
Peak memory	201068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868709303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1868709303
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/29.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.557624790
Short name	T239
Test name
Test status
Simulation time	521851763 ps
CPU time	1.68 seconds
Started	Feb 09 04:03:26 AM UTC 25
Finished	Feb 09 04:03:29 AM UTC 25
Peak memory	199548 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557624790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 29.aon_timer_smoke.557624790
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/29.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.2569462052
Short name	T16
Test name
Test status
Simulation time	31231261906 ps
CPU time	22.57 seconds
Started	Feb 09 03:54:50 AM UTC 25
Finished	Feb 09 03:55:15 AM UTC 25
Peak memory	200996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569462052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2569462052
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.633591014
Short name	T26
Test name
Test status
Simulation time	8231002707 ps
CPU time	20.35 seconds
Started	Feb 09 03:54:55 AM UTC 25
Finished	Feb 09 03:55:16 AM UTC 25
Peak memory	231676 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633591014 -assert nopostproc +UVM_TESTNAME=aon_timer_bas e_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.633591014
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.2877917041
Short name	T7
Test name
Test status
Simulation time	379071040 ps
CPU time	1.27 seconds
Started	Feb 09 03:54:47 AM UTC 25
Finished	Feb 09 03:54:50 AM UTC 25
Peak memory	199484 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877917041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2877917041
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.2908755371
Short name	T243
Test name
Test status
Simulation time	36046825825 ps
CPU time	24.98 seconds
Started	Feb 09 04:03:47 AM UTC 25
Finished	Feb 09 04:04:13 AM UTC 25
Peak memory	200812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908755371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2908755371
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/30.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.3101120100
Short name	T240
Test name
Test status
Simulation time	425144866 ps
CPU time	1.37 seconds
Started	Feb 09 04:03:46 AM UTC 25
Finished	Feb 09 04:03:49 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101120100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3101120100
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/30.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.2972329318
Short name	T193
Test name
Test status
Simulation time	581098403 ps
CPU time	0.99 seconds
Started	Feb 09 04:03:55 AM UTC 25
Finished	Feb 09 04:03:58 AM UTC 25
Peak memory	199540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972329318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 31.aon_timer_jump.2972329318
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/31.aon_timer_jump/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.2004133536
Short name	T244
Test name
Test status
Simulation time	30953516796 ps
CPU time	20.35 seconds
Started	Feb 09 04:03:53 AM UTC 25
Finished	Feb 09 04:04:15 AM UTC 25
Peak memory	201004 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004133536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2004133536
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/31.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.3667840864
Short name	T241
Test name
Test status
Simulation time	563118743 ps
CPU time	1.34 seconds
Started	Feb 09 04:03:52 AM UTC 25
Finished	Feb 09 04:03:55 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667840864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3667840864
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/31.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.2306614573
Short name	T246
Test name
Test status
Simulation time	24187985799 ps
CPU time	25.91 seconds
Started	Feb 09 04:04:03 AM UTC 25
Finished	Feb 09 04:04:30 AM UTC 25
Peak memory	200812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306614573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2306614573
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/32.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.3152807769
Short name	T242
Test name
Test status
Simulation time	475808774 ps
CPU time	0.86 seconds
Started	Feb 09 04:04:02 AM UTC 25
Finished	Feb 09 04:04:04 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152807769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3152807769
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/32.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.2680054005
Short name	T249
Test name
Test status
Simulation time	33204287413 ps
CPU time	53.47 seconds
Started	Feb 09 04:04:21 AM UTC 25
Finished	Feb 09 04:05:16 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680054005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2680054005
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/33.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.1791594258
Short name	T245
Test name
Test status
Simulation time	522757139 ps
CPU time	2.87 seconds
Started	Feb 09 04:04:16 AM UTC 25
Finished	Feb 09 04:04:20 AM UTC 25
Peak memory	200684 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791594258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1791594258
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/33.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.1277730844
Short name	T251
Test name
Test status
Simulation time	16285000019 ps
CPU time	53.18 seconds
Started	Feb 09 04:04:35 AM UTC 25
Finished	Feb 09 04:05:30 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277730844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1277730844
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/34.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.1153662479
Short name	T247
Test name
Test status
Simulation time	538660350 ps
CPU time	1.29 seconds
Started	Feb 09 04:04:32 AM UTC 25
Finished	Feb 09 04:04:35 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153662479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1153662479
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/34.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.538714636
Short name	T253
Test name
Test status
Simulation time	12005430182 ps
CPU time	20.86 seconds
Started	Feb 09 04:05:17 AM UTC 25
Finished	Feb 09 04:05:39 AM UTC 25
Peak memory	200732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538714636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.538714636
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/35.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.1513294180
Short name	T250
Test name
Test status
Simulation time	555957652 ps
CPU time	2.58 seconds
Started	Feb 09 04:05:17 AM UTC 25
Finished	Feb 09 04:05:20 AM UTC 25
Peak memory	200684 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513294180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1513294180
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/35.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.3556085527
Short name	T259
Test name
Test status
Simulation time	38501810448 ps
CPU time	95.79 seconds
Started	Feb 09 04:05:34 AM UTC 25
Finished	Feb 09 04:07:12 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556085527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3556085527
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/36.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.385891020
Short name	T252
Test name
Test status
Simulation time	438811815 ps
CPU time	1.55 seconds
Started	Feb 09 04:05:31 AM UTC 25
Finished	Feb 09 04:05:34 AM UTC 25
Peak memory	199548 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385891020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 36.aon_timer_smoke.385891020
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/36.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.1562932920
Short name	T88
Test name
Test status
Simulation time	1154136058 ps
CPU time	5 seconds
Started	Feb 09 04:05:40 AM UTC 25
Finished	Feb 09 04:05:47 AM UTC 25
Peak memory	200612 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562932920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1562932920
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/37.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.2690496031
Short name	T83
Test name
Test status
Simulation time	433455558 ps
CPU time	2.26 seconds
Started	Feb 09 04:05:38 AM UTC 25
Finished	Feb 09 04:05:42 AM UTC 25
Peak memory	200608 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690496031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2690496031
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/37.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.1609448525
Short name	T254
Test name
Test status
Simulation time	6798000170 ps
CPU time	12.14 seconds
Started	Feb 09 04:05:45 AM UTC 25
Finished	Feb 09 04:05:58 AM UTC 25
Peak memory	200940 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609448525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1609448525
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/38.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.1926107265
Short name	T87
Test name
Test status
Simulation time	491253151 ps
CPU time	1.12 seconds
Started	Feb 09 04:05:43 AM UTC 25
Finished	Feb 09 04:05:46 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926107265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1926107265
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/38.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.1451072658
Short name	T256
Test name
Test status
Simulation time	44429436936 ps
CPU time	25.46 seconds
Started	Feb 09 04:05:55 AM UTC 25
Finished	Feb 09 04:06:22 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451072658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1451072658
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/39.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.467420361
Short name	T91
Test name
Test status
Simulation time	384780020 ps
CPU time	1.39 seconds
Started	Feb 09 04:05:52 AM UTC 25
Finished	Feb 09 04:05:54 AM UTC 25
Peak memory	199548 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467420361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 39.aon_timer_smoke.467420361
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/39.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.318925745
Short name	T60
Test name
Test status
Simulation time	60999876054 ps
CPU time	112.43 seconds
Started	Feb 09 03:54:58 AM UTC 25
Finished	Feb 09 03:56:52 AM UTC 25
Peak memory	201000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318925745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.318925745
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.3666028693
Short name	T27
Test name
Test status
Simulation time	8046331995 ps
CPU time	29.81 seconds
Started	Feb 09 03:55:10 AM UTC 25
Finished	Feb 09 03:55:41 AM UTC 25
Peak memory	231868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666028693 -assert nopostproc +UVM_TESTNAME=aon_timer_ba se_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3666028693
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.2327788227
Short name	T13
Test name
Test status
Simulation time	642319105 ps
CPU time	1.07 seconds
Started	Feb 09 03:54:55 AM UTC 25
Finished	Feb 09 03:54:57 AM UTC 25
Peak memory	199484 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327788227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2327788227
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.1661664667
Short name	T263
Test name
Test status
Simulation time	46865010922 ps
CPU time	90.07 seconds
Started	Feb 09 04:06:13 AM UTC 25
Finished	Feb 09 04:07:45 AM UTC 25
Peak memory	201004 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661664667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1661664667
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/40.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.2066469846
Short name	T255
Test name
Test status
Simulation time	443750163 ps
CPU time	1.36 seconds
Started	Feb 09 04:06:09 AM UTC 25
Finished	Feb 09 04:06:11 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066469846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2066469846
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/40.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.3623455900
Short name	T258
Test name
Test status
Simulation time	23473840919 ps
CPU time	17.31 seconds
Started	Feb 09 04:06:26 AM UTC 25
Finished	Feb 09 04:06:44 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623455900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3623455900
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/41.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.2494677856
Short name	T257
Test name
Test status
Simulation time	447028630 ps
CPU time	1.44 seconds
Started	Feb 09 04:06:23 AM UTC 25
Finished	Feb 09 04:06:25 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494677856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2494677856
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/41.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.1605483733
Short name	T261
Test name
Test status
Simulation time	12524977207 ps
CPU time	6.29 seconds
Started	Feb 09 04:07:16 AM UTC 25
Finished	Feb 09 04:07:24 AM UTC 25
Peak memory	200812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605483733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1605483733
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/42.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.548668066
Short name	T260
Test name
Test status
Simulation time	513730940 ps
CPU time	1.61 seconds
Started	Feb 09 04:07:13 AM UTC 25
Finished	Feb 09 04:07:16 AM UTC 25
Peak memory	199548 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548668066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 42.aon_timer_smoke.548668066
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/42.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.1593809989
Short name	T265
Test name
Test status
Simulation time	59518158981 ps
CPU time	43.05 seconds
Started	Feb 09 04:07:31 AM UTC 25
Finished	Feb 09 04:08:15 AM UTC 25
Peak memory	200812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593809989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1593809989
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/43.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.2489182614
Short name	T262
Test name
Test status
Simulation time	550677267 ps
CPU time	1.04 seconds
Started	Feb 09 04:07:27 AM UTC 25
Finished	Feb 09 04:07:30 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489182614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2489182614
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/43.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all.251826056
Short name	T276
Test name
Test status
Simulation time	144750508592 ps
CPU time	150.44 seconds
Started	Feb 09 04:07:46 AM UTC 25
Finished	Feb 09 04:10:18 AM UTC 25
Peak memory	200808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251826056 -assert nopostproc +UVM_TESTNAME=aon_timer _base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ao n_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all.251826056
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/43.aon_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.1018215838
Short name	T267
Test name
Test status
Simulation time	23543696146 ps
CPU time	36.23 seconds
Started	Feb 09 04:08:05 AM UTC 25
Finished	Feb 09 04:08:43 AM UTC 25
Peak memory	201068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018215838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1018215838
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/44.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.3621234725
Short name	T264
Test name
Test status
Simulation time	417695202 ps
CPU time	1.59 seconds
Started	Feb 09 04:08:03 AM UTC 25
Finished	Feb 09 04:08:06 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621234725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3621234725
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/44.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.2038203926
Short name	T270
Test name
Test status
Simulation time	20451070969 ps
CPU time	36.73 seconds
Started	Feb 09 04:08:26 AM UTC 25
Finished	Feb 09 04:09:04 AM UTC 25
Peak memory	200812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038203926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2038203926
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/45.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.2889677036
Short name	T266
Test name
Test status
Simulation time	469942552 ps
CPU time	1.25 seconds
Started	Feb 09 04:08:23 AM UTC 25
Finished	Feb 09 04:08:26 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889677036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2889677036
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/45.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.2089455191
Short name	T271
Test name
Test status
Simulation time	24038775020 ps
CPU time	18.79 seconds
Started	Feb 09 04:08:45 AM UTC 25
Finished	Feb 09 04:09:05 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089455191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2089455191
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/46.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.957444769
Short name	T268
Test name
Test status
Simulation time	467986590 ps
CPU time	2.17 seconds
Started	Feb 09 04:08:43 AM UTC 25
Finished	Feb 09 04:08:46 AM UTC 25
Peak memory	200612 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957444769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 46.aon_timer_smoke.957444769
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/46.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.1060488233
Short name	T273
Test name
Test status
Simulation time	27778183812 ps
CPU time	49.1 seconds
Started	Feb 09 04:08:59 AM UTC 25
Finished	Feb 09 04:09:50 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060488233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1060488233
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/47.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.3125656229
Short name	T269
Test name
Test status
Simulation time	494095404 ps
CPU time	1.26 seconds
Started	Feb 09 04:08:56 AM UTC 25
Finished	Feb 09 04:08:59 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125656229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3125656229
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/47.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.3069562762
Short name	T275
Test name
Test status
Simulation time	29794970267 ps
CPU time	29.29 seconds
Started	Feb 09 04:09:38 AM UTC 25
Finished	Feb 09 04:10:09 AM UTC 25
Peak memory	200812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069562762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3069562762
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/48.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.1470697805
Short name	T272
Test name
Test status
Simulation time	510950691 ps
CPU time	1.26 seconds
Started	Feb 09 04:09:34 AM UTC 25
Finished	Feb 09 04:09:37 AM UTC 25
Peak memory	199544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470697805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1470697805
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/48.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.2005942778
Short name	T277
Test name
Test status
Simulation time	37122961444 ps
CPU time	27.6 seconds
Started	Feb 09 04:10:01 AM UTC 25
Finished	Feb 09 04:10:30 AM UTC 25
Peak memory	201004 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005942778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2005942778
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/49.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.723379240
Short name	T274
Test name
Test status
Simulation time	505752649 ps
CPU time	1.21 seconds
Started	Feb 09 04:09:58 AM UTC 25
Finished	Feb 09 04:10:00 AM UTC 25
Peak memory	199548 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723379240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 49.aon_timer_smoke.723379240
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/49.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.219295030
Short name	T59
Test name
Test status
Simulation time	48677406014 ps
CPU time	43.49 seconds
Started	Feb 09 03:55:17 AM UTC 25
Finished	Feb 09 03:56:02 AM UTC 25
Peak memory	201064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219295030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.219295030
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.3658421394
Short name	T218
Test name
Test status
Simulation time	595949885 ps
CPU time	1.37 seconds
Started	Feb 09 03:55:15 AM UTC 25
Finished	Feb 09 03:55:17 AM UTC 25
Peak memory	199484 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658421394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3658421394
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.3781243268
Short name	T204
Test name
Test status
Simulation time	5061546250 ps
CPU time	10.24 seconds
Started	Feb 09 03:55:40 AM UTC 25
Finished	Feb 09 03:55:52 AM UTC 25
Peak memory	200740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781243268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3781243268
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.3214511562
Short name	T28
Test name
Test status
Simulation time	385316849 ps
CPU time	1.17 seconds
Started	Feb 09 03:55:37 AM UTC 25
Finished	Feb 09 03:55:40 AM UTC 25
Peak memory	199484 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214511562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3214511562
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.1241178839
Short name	T215
Test name
Test status
Simulation time	59211678373 ps
CPU time	90.47 seconds
Started	Feb 09 03:55:49 AM UTC 25
Finished	Feb 09 03:57:21 AM UTC 25
Peak memory	200732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241178839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1241178839
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.2592309262
Short name	T219
Test name
Test status
Simulation time	500528345 ps
CPU time	1.26 seconds
Started	Feb 09 03:55:46 AM UTC 25
Finished	Feb 09 03:55:48 AM UTC 25
Peak memory	199484 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592309262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2592309262
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.565026269
Short name	T208
Test name
Test status
Simulation time	26380689364 ps
CPU time	84.09 seconds
Started	Feb 09 03:56:25 AM UTC 25
Finished	Feb 09 03:57:51 AM UTC 25
Peak memory	201000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565026269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_ timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.565026269
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.1411706504
Short name	T19
Test name
Test status
Simulation time	429578328 ps
CPU time	2.17 seconds
Started	Feb 09 03:56:21 AM UTC 25
Finished	Feb 09 03:56:24 AM UTC 25
Peak memory	200612 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411706504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1411706504
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.2455278560
Short name	T214
Test name
Test status
Simulation time	53509017951 ps
CPU time	106.61 seconds
Started	Feb 09 03:56:50 AM UTC 25
Finished	Feb 09 03:58:39 AM UTC 25
Peak memory	200804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455278560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2455278560
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_prescaler/latest

Test location	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.2563899830
Short name	T220
Test name
Test status
Simulation time	554085056 ps
CPU time	1.33 seconds
Started	Feb 09 03:56:47 AM UTC 25
Finished	Feb 09 03:56:50 AM UTC 25
Peak memory	199484 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563899830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2563899830
Directory	/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_smoke/latest