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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.49 99.32 95.61 100.00 98.38 99.51 44.13


Total test records in report: 416
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T124 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.1222636187 Oct 14 10:08:32 PM UTC 24 Oct 14 10:21:43 PM UTC 24 495704875447 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.3287609736 Oct 14 08:55:45 PM UTC 24 Oct 14 08:55:47 PM UTC 24 511126766 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.3567454319 Oct 14 08:55:45 PM UTC 24 Oct 14 08:55:47 PM UTC 24 331227060 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.964797553 Oct 14 08:55:45 PM UTC 24 Oct 14 08:55:47 PM UTC 24 279049272 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.471241671 Oct 14 08:55:45 PM UTC 24 Oct 14 08:55:47 PM UTC 24 739612861 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.3010867049 Oct 14 08:55:45 PM UTC 24 Oct 14 08:55:48 PM UTC 24 476651256 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1724546815 Oct 14 08:55:46 PM UTC 24 Oct 14 08:55:48 PM UTC 24 509131501 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.408867186 Oct 14 08:55:45 PM UTC 24 Oct 14 08:55:49 PM UTC 24 377202632 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3325070491 Oct 14 08:55:48 PM UTC 24 Oct 14 08:55:50 PM UTC 24 317328664 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3781097930 Oct 14 08:55:48 PM UTC 24 Oct 14 08:55:51 PM UTC 24 1360790701 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.3020373292 Oct 14 08:55:48 PM UTC 24 Oct 14 08:55:51 PM UTC 24 666267657 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.4085551171 Oct 14 08:55:49 PM UTC 24 Oct 14 08:55:51 PM UTC 24 402585390 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2857980471 Oct 14 08:55:50 PM UTC 24 Oct 14 08:55:51 PM UTC 24 725880759 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.1008769872 Oct 14 08:55:49 PM UTC 24 Oct 14 08:55:51 PM UTC 24 302995451 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1012848064 Oct 14 08:55:50 PM UTC 24 Oct 14 08:55:52 PM UTC 24 472551456 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2220352605 Oct 14 08:55:45 PM UTC 24 Oct 14 08:55:52 PM UTC 24 3959943591 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2942602358 Oct 14 08:55:49 PM UTC 24 Oct 14 08:55:52 PM UTC 24 4876462340 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.3306081696 Oct 14 08:55:52 PM UTC 24 Oct 14 08:55:54 PM UTC 24 404841707 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2211785188 Oct 14 08:55:53 PM UTC 24 Oct 14 08:55:54 PM UTC 24 375372339 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.1898565192 Oct 14 08:55:53 PM UTC 24 Oct 14 08:55:55 PM UTC 24 279699458 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.957878359 Oct 14 08:55:53 PM UTC 24 Oct 14 08:55:55 PM UTC 24 318572616 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.1754934862 Oct 14 08:55:53 PM UTC 24 Oct 14 08:55:55 PM UTC 24 288405417 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2652171678 Oct 14 08:55:53 PM UTC 24 Oct 14 08:55:55 PM UTC 24 1128556453 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.75420486 Oct 14 08:55:53 PM UTC 24 Oct 14 08:55:55 PM UTC 24 5554836284 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.3518049435 Oct 14 08:55:53 PM UTC 24 Oct 14 08:55:56 PM UTC 24 350339882 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.645922293 Oct 14 08:55:54 PM UTC 24 Oct 14 08:55:56 PM UTC 24 852706082 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3350487983 Oct 14 08:55:54 PM UTC 24 Oct 14 08:55:56 PM UTC 24 523340563 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4227413997 Oct 14 08:55:45 PM UTC 24 Oct 14 08:55:56 PM UTC 24 14087276844 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3566411060 Oct 14 08:55:55 PM UTC 24 Oct 14 08:55:57 PM UTC 24 603035304 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.4055236253 Oct 14 08:55:55 PM UTC 24 Oct 14 08:55:57 PM UTC 24 389711701 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.2956251530 Oct 14 08:55:56 PM UTC 24 Oct 14 08:55:58 PM UTC 24 427091609 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.70484204 Oct 14 08:55:56 PM UTC 24 Oct 14 08:55:58 PM UTC 24 297608102 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.409679737 Oct 14 08:55:55 PM UTC 24 Oct 14 08:55:58 PM UTC 24 1148161366 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.1698706725 Oct 14 08:55:56 PM UTC 24 Oct 14 08:55:58 PM UTC 24 496822959 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.94222984 Oct 14 08:55:56 PM UTC 24 Oct 14 08:55:59 PM UTC 24 519045676 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1417081705 Oct 14 08:55:57 PM UTC 24 Oct 14 08:55:59 PM UTC 24 461665354 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.42195551 Oct 14 08:55:57 PM UTC 24 Oct 14 08:56:00 PM UTC 24 470934716 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3501027353 Oct 14 08:55:53 PM UTC 24 Oct 14 08:56:00 PM UTC 24 4002956240 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2564020531 Oct 14 08:55:58 PM UTC 24 Oct 14 08:56:00 PM UTC 24 460860170 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2556634451 Oct 14 08:55:57 PM UTC 24 Oct 14 08:56:00 PM UTC 24 1057245441 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1961622821 Oct 14 08:55:59 PM UTC 24 Oct 14 08:56:02 PM UTC 24 451431458 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2510262511 Oct 14 08:55:59 PM UTC 24 Oct 14 08:56:02 PM UTC 24 1821814213 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.1038222464 Oct 14 08:56:00 PM UTC 24 Oct 14 08:56:02 PM UTC 24 1171144822 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.380656659 Oct 14 08:56:01 PM UTC 24 Oct 14 08:56:02 PM UTC 24 376500198 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2662771776 Oct 14 08:56:01 PM UTC 24 Oct 14 08:56:02 PM UTC 24 1255029011 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.1693447817 Oct 14 08:56:01 PM UTC 24 Oct 14 08:56:03 PM UTC 24 310463944 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.1407609619 Oct 14 08:56:01 PM UTC 24 Oct 14 08:56:03 PM UTC 24 470674613 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3281218956 Oct 14 08:55:56 PM UTC 24 Oct 14 08:56:04 PM UTC 24 8141593510 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3409642218 Oct 14 08:56:00 PM UTC 24 Oct 14 08:56:05 PM UTC 24 8409473911 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1479956866 Oct 14 08:56:03 PM UTC 24 Oct 14 08:56:05 PM UTC 24 1411804744 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3640885169 Oct 14 08:56:03 PM UTC 24 Oct 14 08:56:05 PM UTC 24 474622652 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3833469135 Oct 14 08:56:03 PM UTC 24 Oct 14 08:56:05 PM UTC 24 509857260 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.2366648352 Oct 14 08:56:03 PM UTC 24 Oct 14 08:56:05 PM UTC 24 345496881 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.3202840092 Oct 14 08:56:03 PM UTC 24 Oct 14 08:56:05 PM UTC 24 467623171 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.312622296 Oct 14 08:56:03 PM UTC 24 Oct 14 08:56:05 PM UTC 24 496727473 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3836042549 Oct 14 08:56:03 PM UTC 24 Oct 14 08:56:06 PM UTC 24 1053725413 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.2063656221 Oct 14 08:56:03 PM UTC 24 Oct 14 08:56:06 PM UTC 24 473980746 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1523613778 Oct 14 08:56:03 PM UTC 24 Oct 14 08:56:06 PM UTC 24 4599773232 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.3883214000 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:07 PM UTC 24 543499369 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.1362168915 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:07 PM UTC 24 403139054 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3602504986 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:07 PM UTC 24 416148703 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3386271104 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:07 PM UTC 24 999573219 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.3257609835 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:07 PM UTC 24 360927110 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.64448027 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:07 PM UTC 24 304833761 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.1873704001 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:07 PM UTC 24 316626551 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.4247380448 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:07 PM UTC 24 374659937 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2806438342 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:07 PM UTC 24 475147983 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1892858132 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:07 PM UTC 24 465877525 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.1464977599 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:08 PM UTC 24 499506041 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.3477564141 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:08 PM UTC 24 941285816 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3888886628 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:08 PM UTC 24 533409669 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3571338727 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:08 PM UTC 24 1534039360 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.1676498676 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:09 PM UTC 24 527601336 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.964175474 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:09 PM UTC 24 362958654 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2221163176 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:09 PM UTC 24 2043263756 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2664543510 Oct 14 08:55:55 PM UTC 24 Oct 14 08:56:09 PM UTC 24 7018797145 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3616123585 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:10 PM UTC 24 2677735336 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.209629734 Oct 14 08:55:58 PM UTC 24 Oct 14 08:56:12 PM UTC 24 5623803847 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1535415529 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:12 PM UTC 24 4638760507 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2625724964 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:12 PM UTC 24 3954237110 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1140416707 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:12 PM UTC 24 4462798431 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.2434096651 Oct 14 08:56:12 PM UTC 24 Oct 14 08:56:14 PM UTC 24 411166169 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.3255613899 Oct 14 08:56:12 PM UTC 24 Oct 14 08:56:14 PM UTC 24 502584541 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.3893566533 Oct 14 08:56:12 PM UTC 24 Oct 14 08:56:14 PM UTC 24 396209423 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.2657712194 Oct 14 08:56:12 PM UTC 24 Oct 14 08:56:14 PM UTC 24 318165369 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.456575388 Oct 14 08:56:12 PM UTC 24 Oct 14 08:56:14 PM UTC 24 492996844 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.805365062 Oct 14 08:56:12 PM UTC 24 Oct 14 08:56:15 PM UTC 24 2248157726 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.730892849 Oct 14 08:56:12 PM UTC 24 Oct 14 08:56:15 PM UTC 24 416125014 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.3978256220 Oct 14 08:56:12 PM UTC 24 Oct 14 08:56:15 PM UTC 24 337821647 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1721798981 Oct 14 08:56:12 PM UTC 24 Oct 14 08:56:15 PM UTC 24 494106067 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.463221789 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:15 PM UTC 24 372336007 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2877459104 Oct 14 08:56:05 PM UTC 24 Oct 14 08:56:15 PM UTC 24 8491699120 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.3291885372 Oct 14 08:56:16 PM UTC 24 Oct 14 08:56:31 PM UTC 24 321274677 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.47286200 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:15 PM UTC 24 331831337 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.1306232852 Oct 14 08:56:16 PM UTC 24 Oct 14 08:56:31 PM UTC 24 424246482 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.1832228843 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:15 PM UTC 24 351801321 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.334357104 Oct 14 08:56:16 PM UTC 24 Oct 14 08:56:31 PM UTC 24 316585786 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1511559187 Oct 14 08:56:12 PM UTC 24 Oct 14 08:56:15 PM UTC 24 2329196757 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1208122487 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:15 PM UTC 24 315477939 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.26465940 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:15 PM UTC 24 359594043 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1454872266 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:15 PM UTC 24 444156261 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1284772944 Oct 14 08:56:12 PM UTC 24 Oct 14 08:56:15 PM UTC 24 4550826684 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.2778677905 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:15 PM UTC 24 356205781 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.3111439188 Oct 14 08:56:16 PM UTC 24 Oct 14 08:56:31 PM UTC 24 275704613 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.3905310740 Oct 14 08:56:12 PM UTC 24 Oct 14 08:56:15 PM UTC 24 569177502 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1111744910 Oct 14 08:56:15 PM UTC 24 Oct 14 08:56:26 PM UTC 24 8529479623 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1714453917 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:15 PM UTC 24 464698136 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.3148050934 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:15 PM UTC 24 426205560 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.1271878119 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:15 PM UTC 24 443751537 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.3453711274 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:15 PM UTC 24 403876828 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.1133516780 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:15 PM UTC 24 470171688 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2922967031 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:22 PM UTC 24 4398371603 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.346776124 Oct 14 08:56:16 PM UTC 24 Oct 14 08:56:32 PM UTC 24 509375584 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.323880753 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:15 PM UTC 24 280898952 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3753593247 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:15 PM UTC 24 475978201 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.762748505 Oct 14 08:56:14 PM UTC 24 Oct 14 08:56:15 PM UTC 24 420848537 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.4218938758 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:16 PM UTC 24 372302122 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.2907442587 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:16 PM UTC 24 394734726 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.241689288 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:16 PM UTC 24 318517677 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3794081244 Oct 14 08:56:12 PM UTC 24 Oct 14 08:56:16 PM UTC 24 4287990053 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.1879050934 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:16 PM UTC 24 455891102 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.2124921458 Oct 14 08:56:14 PM UTC 24 Oct 14 08:56:16 PM UTC 24 338776050 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.2908101309 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:16 PM UTC 24 351916212 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.2454324385 Oct 14 08:56:12 PM UTC 24 Oct 14 08:56:16 PM UTC 24 972179435 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.243634600 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:16 PM UTC 24 2490584842 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3082646580 Oct 14 08:56:14 PM UTC 24 Oct 14 08:56:16 PM UTC 24 536418673 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1869216742 Oct 14 08:56:14 PM UTC 24 Oct 14 08:56:16 PM UTC 24 1370023004 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3127069284 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:16 PM UTC 24 500248966 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.3590189722 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:16 PM UTC 24 365289248 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.919670763 Oct 14 08:56:14 PM UTC 24 Oct 14 08:56:16 PM UTC 24 410506376 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.3023395122 Oct 14 08:56:14 PM UTC 24 Oct 14 08:56:16 PM UTC 24 531206301 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.800501674 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:16 PM UTC 24 571788318 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2100800006 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:16 PM UTC 24 1472097071 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1664384216 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:16 PM UTC 24 9861789494 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.799474014 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:17 PM UTC 24 2086655321 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.2619244787 Oct 14 08:56:15 PM UTC 24 Oct 14 08:56:17 PM UTC 24 484662325 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.355025047 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:17 PM UTC 24 4016253441 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2955800427 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:17 PM UTC 24 1482952713 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.94232483 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:17 PM UTC 24 542735182 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1824369916 Oct 14 08:56:15 PM UTC 24 Oct 14 08:56:17 PM UTC 24 398614383 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1852501796 Oct 14 08:56:15 PM UTC 24 Oct 14 08:56:17 PM UTC 24 366676941 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.172167506 Oct 14 08:56:15 PM UTC 24 Oct 14 08:56:17 PM UTC 24 529965769 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.310995906 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:17 PM UTC 24 4439034602 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.2326064024 Oct 14 08:56:15 PM UTC 24 Oct 14 08:56:17 PM UTC 24 476568440 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2187567662 Oct 14 08:56:14 PM UTC 24 Oct 14 08:56:18 PM UTC 24 2248452091 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.353437951 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:18 PM UTC 24 2861977825 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.2845540416 Oct 14 08:56:16 PM UTC 24 Oct 14 08:56:18 PM UTC 24 317188485 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.108877884 Oct 14 08:56:16 PM UTC 24 Oct 14 08:56:18 PM UTC 24 500031747 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.4189492976 Oct 14 08:56:16 PM UTC 24 Oct 14 08:56:18 PM UTC 24 313177081 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1478890406 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:18 PM UTC 24 2511212477 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1791858708 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:18 PM UTC 24 8717752616 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.2161845769 Oct 14 08:56:15 PM UTC 24 Oct 14 08:56:18 PM UTC 24 530828562 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.3563059116 Oct 14 08:56:16 PM UTC 24 Oct 14 08:56:19 PM UTC 24 490442275 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2081818308 Oct 14 08:56:14 PM UTC 24 Oct 14 08:56:19 PM UTC 24 8617024205 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4222068890 Oct 14 08:56:15 PM UTC 24 Oct 14 08:56:20 PM UTC 24 2404881427 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2119177160 Oct 14 08:56:13 PM UTC 24 Oct 14 08:56:20 PM UTC 24 3844999269 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.723043573 Oct 14 08:56:16 PM UTC 24 Oct 14 08:56:31 PM UTC 24 338151151 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.1122346226 Oct 14 08:56:16 PM UTC 24 Oct 14 08:56:32 PM UTC 24 407664520 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2712463396 Oct 14 08:56:16 PM UTC 24 Oct 14 08:56:32 PM UTC 24 498058338 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.3393795976 Oct 14 08:56:16 PM UTC 24 Oct 14 08:56:32 PM UTC 24 459568663 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.3667034630 Oct 14 08:56:17 PM UTC 24 Oct 14 08:56:42 PM UTC 24 433171738 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.4245019094 Oct 14 08:56:17 PM UTC 24 Oct 14 08:56:42 PM UTC 24 482147070 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.3936210332 Oct 14 08:56:17 PM UTC 24 Oct 14 08:56:42 PM UTC 24 362456209 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.2734495297 Oct 14 08:56:17 PM UTC 24 Oct 14 08:56:42 PM UTC 24 314713082 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.1659115632 Oct 14 08:56:17 PM UTC 24 Oct 14 08:56:42 PM UTC 24 440415910 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.2128631316 Oct 14 08:56:17 PM UTC 24 Oct 14 08:56:50 PM UTC 24 368634845 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.750864567
Short name T7
Test name
Test status
Simulation time 579504439 ps
CPU time 2.83 seconds
Started Oct 14 10:07:06 PM UTC 24
Finished Oct 14 10:07:09 PM UTC 24
Peak memory 203476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750864567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.750864567
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all_with_rand_reset.1351687244
Short name T23
Test name
Test status
Simulation time 3124598802 ps
CPU time 30.71 seconds
Started Oct 14 10:07:07 PM UTC 24
Finished Oct 14 10:07:39 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1351687244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 2.aon_timer_stress_all_with_rand_reset.1351687244
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2942602358
Short name T40
Test name
Test status
Simulation time 4876462340 ps
CPU time 1.98 seconds
Started Oct 14 08:55:49 PM UTC 24
Finished Oct 14 08:55:52 PM UTC 24
Peak memory 199628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942602358 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.2942602358
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all_with_rand_reset.3620565512
Short name T45
Test name
Test status
Simulation time 6578190155 ps
CPU time 40.07 seconds
Started Oct 14 10:07:30 PM UTC 24
Finished Oct 14 10:08:12 PM UTC 24
Peak memory 209088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3620565512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 6.aon_timer_stress_all_with_rand_reset.3620565512
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all.2345279551
Short name T1
Test name
Test status
Simulation time 61293988819 ps
CPU time 100.67 seconds
Started Oct 14 10:07:08 PM UTC 24
Finished Oct 14 10:08:50 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345279551 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.2345279551
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all_with_rand_reset.2830461134
Short name T96
Test name
Test status
Simulation time 16881551850 ps
CPU time 40.21 seconds
Started Oct 14 10:11:35 PM UTC 24
Finished Oct 14 10:12:17 PM UTC 24
Peak memory 208976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2830461134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 43.aon_timer_stress_all_with_rand_reset.2830461134
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1724546815
Short name T37
Test name
Test status
Simulation time 509131501 ps
CPU time 0.8 seconds
Started Oct 14 08:55:46 PM UTC 24
Finished Oct 14 08:55:48 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724546815 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.1724546815
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all.712119028
Short name T85
Test name
Test status
Simulation time 18623121432 ps
CPU time 35.6 seconds
Started Oct 14 10:09:16 PM UTC 24
Finished Oct 14 10:09:53 PM UTC 24
Peak memory 203268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712119028 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all.712119028
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/22.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.1273951786
Short name T170
Test name
Test status
Simulation time 20315390934 ps
CPU time 55.42 seconds
Started Oct 14 10:10:14 PM UTC 24
Finished Oct 14 10:11:11 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1273951786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 30.aon_timer_stress_all_with_rand_reset.1273951786
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.768810981
Short name T11
Test name
Test status
Simulation time 7438391725 ps
CPU time 3.6 seconds
Started Oct 14 10:07:03 PM UTC 24
Finished Oct 14 10:07:08 PM UTC 24
Peak memory 233880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768810981 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.768810981
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all.1112515669
Short name T25
Test name
Test status
Simulation time 47360876263 ps
CPU time 26.2 seconds
Started Oct 14 10:07:23 PM UTC 24
Finished Oct 14 10:07:51 PM UTC 24
Peak memory 203668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112515669 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all.1112515669
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/5.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all.1646264174
Short name T88
Test name
Test status
Simulation time 144865357424 ps
CPU time 223.21 seconds
Started Oct 14 10:09:11 PM UTC 24
Finished Oct 14 10:12:57 PM UTC 24
Peak memory 203348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646264174 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all.1646264174
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/21.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all.4077243457
Short name T98
Test name
Test status
Simulation time 490984678722 ps
CPU time 146.17 seconds
Started Oct 14 10:10:01 PM UTC 24
Finished Oct 14 10:12:29 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077243457 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all.4077243457
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/27.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all_with_rand_reset.2236806775
Short name T112
Test name
Test status
Simulation time 2987738349 ps
CPU time 25.13 seconds
Started Oct 14 10:11:52 PM UTC 24
Finished Oct 14 10:12:18 PM UTC 24
Peak memory 212928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2236806775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 46.aon_timer_stress_all_with_rand_reset.2236806775
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all.3415882327
Short name T95
Test name
Test status
Simulation time 104665506834 ps
CPU time 62.24 seconds
Started Oct 14 10:11:03 PM UTC 24
Finished Oct 14 10:12:07 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415882327 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all.3415882327
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/37.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all_with_rand_reset.3059100535
Short name T143
Test name
Test status
Simulation time 6203807034 ps
CPU time 60.36 seconds
Started Oct 14 10:11:54 PM UTC 24
Finished Oct 14 10:12:56 PM UTC 24
Peak memory 217708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3059100535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 47.aon_timer_stress_all_with_rand_reset.3059100535
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all.177261317
Short name T90
Test name
Test status
Simulation time 66496290650 ps
CPU time 181.66 seconds
Started Oct 14 10:08:48 PM UTC 24
Finished Oct 14 10:11:52 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177261317 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all.177261317
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/17.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.4009179439
Short name T91
Test name
Test status
Simulation time 4579263918 ps
CPU time 45.43 seconds
Started Oct 14 10:07:44 PM UTC 24
Finished Oct 14 10:08:31 PM UTC 24
Peak memory 216884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4009179439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 7.aon_timer_stress_all_with_rand_reset.4009179439
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all_with_rand_reset.136123326
Short name T44
Test name
Test status
Simulation time 7620455502 ps
CPU time 60.92 seconds
Started Oct 14 10:07:03 PM UTC 24
Finished Oct 14 10:08:06 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=136123326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 0.aon_timer_stress_all_with_rand_reset.136123326
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all.2300825087
Short name T131
Test name
Test status
Simulation time 75275652533 ps
CPU time 26.71 seconds
Started Oct 14 10:10:53 PM UTC 24
Finished Oct 14 10:11:21 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300825087 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all.2300825087
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/35.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all.1327913940
Short name T109
Test name
Test status
Simulation time 200720181449 ps
CPU time 415.52 seconds
Started Oct 14 10:11:35 PM UTC 24
Finished Oct 14 10:18:36 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327913940 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all.1327913940
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/43.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all_with_rand_reset.1325256489
Short name T123
Test name
Test status
Simulation time 7908893412 ps
CPU time 46.99 seconds
Started Oct 14 10:10:05 PM UTC 24
Finished Oct 14 10:10:54 PM UTC 24
Peak memory 209004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1325256489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 28.aon_timer_stress_all_with_rand_reset.1325256489
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.3488434646
Short name T126
Test name
Test status
Simulation time 208583098130 ps
CPU time 152.13 seconds
Started Oct 14 10:10:27 PM UTC 24
Finished Oct 14 10:13:02 PM UTC 24
Peak memory 203416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488434646 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.3488434646
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/32.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all.2282749052
Short name T142
Test name
Test status
Simulation time 215493053845 ps
CPU time 75.51 seconds
Started Oct 14 10:11:43 PM UTC 24
Finished Oct 14 10:13:00 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282749052 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all.2282749052
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/45.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.410447270
Short name T114
Test name
Test status
Simulation time 175434154609 ps
CPU time 117.29 seconds
Started Oct 14 10:10:41 PM UTC 24
Finished Oct 14 10:12:41 PM UTC 24
Peak memory 203344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410447270 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.410447270
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/34.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.2883456682
Short name T138
Test name
Test status
Simulation time 486772991432 ps
CPU time 827.6 seconds
Started Oct 14 10:07:44 PM UTC 24
Finished Oct 14 10:21:40 PM UTC 24
Peak memory 206636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883456682 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.2883456682
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/7.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.3931872024
Short name T116
Test name
Test status
Simulation time 122633329164 ps
CPU time 55.23 seconds
Started Oct 14 10:11:34 PM UTC 24
Finished Oct 14 10:12:31 PM UTC 24
Peak memory 202484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931872024 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.3931872024
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/42.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all.447229114
Short name T151
Test name
Test status
Simulation time 105853174748 ps
CPU time 181.97 seconds
Started Oct 14 10:08:15 PM UTC 24
Finished Oct 14 10:11:20 PM UTC 24
Peak memory 203344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447229114 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all.447229114
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/12.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all_with_rand_reset.2842650777
Short name T167
Test name
Test status
Simulation time 14321705422 ps
CPU time 29.32 seconds
Started Oct 14 10:10:40 PM UTC 24
Finished Oct 14 10:11:11 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2842650777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 34.aon_timer_stress_all_with_rand_reset.2842650777
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all_with_rand_reset.2573383102
Short name T99
Test name
Test status
Simulation time 7135237348 ps
CPU time 33.85 seconds
Started Oct 14 10:11:06 PM UTC 24
Finished Oct 14 10:11:42 PM UTC 24
Peak memory 221120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2573383102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 38.aon_timer_stress_all_with_rand_reset.2573383102
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all_with_rand_reset.1603527615
Short name T120
Test name
Test status
Simulation time 4191126340 ps
CPU time 34.54 seconds
Started Oct 14 10:11:02 PM UTC 24
Finished Oct 14 10:11:38 PM UTC 24
Peak memory 222060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1603527615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 37.aon_timer_stress_all_with_rand_reset.1603527615
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all_with_rand_reset.1551554778
Short name T93
Test name
Test status
Simulation time 16244793630 ps
CPU time 42.29 seconds
Started Oct 14 10:10:53 PM UTC 24
Finished Oct 14 10:11:37 PM UTC 24
Peak memory 209068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1551554778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 35.aon_timer_stress_all_with_rand_reset.1551554778
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all_with_rand_reset.568623037
Short name T155
Test name
Test status
Simulation time 5930731664 ps
CPU time 39.4 seconds
Started Oct 14 10:10:58 PM UTC 24
Finished Oct 14 10:11:39 PM UTC 24
Peak memory 217712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=568623037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 36.aon_timer_stress_all_with_rand_reset.568623037
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all.1362706563
Short name T125
Test name
Test status
Simulation time 4280183612 ps
CPU time 3.4 seconds
Started Oct 14 10:12:08 PM UTC 24
Finished Oct 14 10:12:12 PM UTC 24
Peak memory 203544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362706563 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all.1362706563
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/49.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.3437534156
Short name T107
Test name
Test status
Simulation time 387768564787 ps
CPU time 97.64 seconds
Started Oct 14 10:11:20 PM UTC 24
Finished Oct 14 10:13:00 PM UTC 24
Peak memory 203284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437534156 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.3437534156
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/40.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all_with_rand_reset.2170847950
Short name T105
Test name
Test status
Simulation time 11062427060 ps
CPU time 27.63 seconds
Started Oct 14 10:09:44 PM UTC 24
Finished Oct 14 10:10:13 PM UTC 24
Peak memory 218056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2170847950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 26.aon_timer_stress_all_with_rand_reset.2170847950
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.3358108909
Short name T115
Test name
Test status
Simulation time 18578436116 ps
CPU time 18.05 seconds
Started Oct 14 10:08:21 PM UTC 24
Finished Oct 14 10:08:41 PM UTC 24
Peak memory 203672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358108909 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.3358108909
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/13.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all.1910264576
Short name T26
Test name
Test status
Simulation time 5336160522 ps
CPU time 19.59 seconds
Started Oct 14 10:07:37 PM UTC 24
Finished Oct 14 10:07:58 PM UTC 24
Peak memory 203600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910264576 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all.1910264576
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/6.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.3777396263
Short name T161
Test name
Test status
Simulation time 333253218977 ps
CPU time 282.38 seconds
Started Oct 14 10:08:03 PM UTC 24
Finished Oct 14 10:12:49 PM UTC 24
Peak memory 203544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777396263 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.3777396263
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/10.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all_with_rand_reset.1344925143
Short name T122
Test name
Test status
Simulation time 1785957801 ps
CPU time 15.3 seconds
Started Oct 14 10:09:27 PM UTC 24
Finished Oct 14 10:09:43 PM UTC 24
Peak memory 209320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1344925143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 24.aon_timer_stress_all_with_rand_reset.1344925143
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.3077817197
Short name T97
Test name
Test status
Simulation time 246699932185 ps
CPU time 100.43 seconds
Started Oct 14 10:10:58 PM UTC 24
Finished Oct 14 10:12:41 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077817197 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.3077817197
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/36.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all_with_rand_reset.633917189
Short name T172
Test name
Test status
Simulation time 14842197528 ps
CPU time 37.82 seconds
Started Oct 14 10:09:14 PM UTC 24
Finished Oct 14 10:09:53 PM UTC 24
Peak memory 217520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=633917189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 22.aon_timer_stress_all_with_rand_reset.633917189
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all.4215575004
Short name T144
Test name
Test status
Simulation time 99655121148 ps
CPU time 88.92 seconds
Started Oct 14 10:09:23 PM UTC 24
Finished Oct 14 10:10:54 PM UTC 24
Peak memory 203672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215575004 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all.4215575004
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/23.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all.3427574564
Short name T102
Test name
Test status
Simulation time 278377878380 ps
CPU time 117.21 seconds
Started Oct 14 10:08:39 PM UTC 24
Finished Oct 14 10:10:38 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427574564 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.3427574564
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/15.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.2816027606
Short name T132
Test name
Test status
Simulation time 300765585003 ps
CPU time 45.09 seconds
Started Oct 14 10:10:22 PM UTC 24
Finished Oct 14 10:11:09 PM UTC 24
Peak memory 203416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816027606 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.2816027606
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/31.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all.2916533548
Short name T134
Test name
Test status
Simulation time 109156453088 ps
CPU time 47.22 seconds
Started Oct 14 10:11:12 PM UTC 24
Finished Oct 14 10:12:01 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916533548 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all.2916533548
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/39.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.343742975
Short name T127
Test name
Test status
Simulation time 29758488635 ps
CPU time 32.49 seconds
Started Oct 14 10:11:52 PM UTC 24
Finished Oct 14 10:12:25 PM UTC 24
Peak memory 203600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343742975 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.343742975
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/46.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all_with_rand_reset.1458944315
Short name T150
Test name
Test status
Simulation time 7420141635 ps
CPU time 44.54 seconds
Started Oct 14 10:08:32 PM UTC 24
Finished Oct 14 10:09:18 PM UTC 24
Peak memory 218364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1458944315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 14.aon_timer_stress_all_with_rand_reset.1458944315
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all.2388161647
Short name T182
Test name
Test status
Simulation time 121883833497 ps
CPU time 168.02 seconds
Started Oct 14 10:08:44 PM UTC 24
Finished Oct 14 10:11:34 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388161647 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.2388161647
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/16.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all.2981825215
Short name T149
Test name
Test status
Simulation time 489996755147 ps
CPU time 165.84 seconds
Started Oct 14 10:11:29 PM UTC 24
Finished Oct 14 10:14:17 PM UTC 24
Peak memory 203608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981825215 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all.2981825215
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/41.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all.3908508270
Short name T110
Test name
Test status
Simulation time 235736306445 ps
CPU time 468.91 seconds
Started Oct 14 10:11:39 PM UTC 24
Finished Oct 14 10:19:33 PM UTC 24
Peak memory 203548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908508270 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all.3908508270
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/44.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.3010867049
Short name T42
Test name
Test status
Simulation time 476651256 ps
CPU time 1.06 seconds
Started Oct 14 08:55:45 PM UTC 24
Finished Oct 14 08:55:48 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010867049 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3010867049
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.1816670366
Short name T176
Test name
Test status
Simulation time 170009193090 ps
CPU time 348.69 seconds
Started Oct 14 10:07:03 PM UTC 24
Finished Oct 14 10:12:56 PM UTC 24
Peak memory 203268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816670366 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.1816670366
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all_with_rand_reset.1102791336
Short name T136
Test name
Test status
Simulation time 2098630648 ps
CPU time 17.87 seconds
Started Oct 14 10:10:21 PM UTC 24
Finished Oct 14 10:10:40 PM UTC 24
Peak memory 216616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1102791336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 31.aon_timer_stress_all_with_rand_reset.1102791336
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.3885012268
Short name T32
Test name
Test status
Simulation time 4257955337 ps
CPU time 26.8 seconds
Started Oct 14 10:07:21 PM UTC 24
Finished Oct 14 10:07:49 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3885012268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 5.aon_timer_stress_all_with_rand_reset.3885012268
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.381544063
Short name T152
Test name
Test status
Simulation time 243407596931 ps
CPU time 181.84 seconds
Started Oct 14 10:07:58 PM UTC 24
Finished Oct 14 10:11:02 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381544063 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.381544063
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/9.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.4155847301
Short name T117
Test name
Test status
Simulation time 269670367730 ps
CPU time 140.85 seconds
Started Oct 14 10:07:03 PM UTC 24
Finished Oct 14 10:09:26 PM UTC 24
Peak memory 203408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155847301 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.4155847301
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all_with_rand_reset.2613266425
Short name T79
Test name
Test status
Simulation time 6131566165 ps
CPU time 30.22 seconds
Started Oct 14 10:08:14 PM UTC 24
Finished Oct 14 10:08:46 PM UTC 24
Peak memory 221064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2613266425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 12.aon_timer_stress_all_with_rand_reset.2613266425
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.2617773350
Short name T94
Test name
Test status
Simulation time 113696910179 ps
CPU time 207.29 seconds
Started Oct 14 10:08:54 PM UTC 24
Finished Oct 14 10:12:25 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617773350 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.2617773350
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/18.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.2854068759
Short name T104
Test name
Test status
Simulation time 161359113182 ps
CPU time 159.46 seconds
Started Oct 14 10:09:47 PM UTC 24
Finished Oct 14 10:12:30 PM UTC 24
Peak memory 203272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854068759 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all.2854068759
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/26.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.3234451860
Short name T156
Test name
Test status
Simulation time 344460205601 ps
CPU time 514.4 seconds
Started Oct 14 10:12:03 PM UTC 24
Finished Oct 14 10:20:43 PM UTC 24
Peak memory 206644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234451860 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.3234451860
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/48.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all_with_rand_reset.2755374504
Short name T17
Test name
Test status
Simulation time 2132424013 ps
CPU time 21.09 seconds
Started Oct 14 10:07:03 PM UTC 24
Finished Oct 14 10:07:26 PM UTC 24
Peak memory 212724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2755374504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 1.aon_timer_stress_all_with_rand_reset.2755374504
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.423511622
Short name T158
Test name
Test status
Simulation time 549518932 ps
CPU time 2.67 seconds
Started Oct 14 10:08:31 PM UTC 24
Finished Oct 14 10:08:35 PM UTC 24
Peak memory 203492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423511622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.423511622
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/14.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.1222636187
Short name T124
Test name
Test status
Simulation time 495704875447 ps
CPU time 783.12 seconds
Started Oct 14 10:08:32 PM UTC 24
Finished Oct 14 10:21:43 PM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222636187 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all.1222636187
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/14.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.3622412085
Short name T147
Test name
Test status
Simulation time 448865777 ps
CPU time 1.24 seconds
Started Oct 14 10:08:51 PM UTC 24
Finished Oct 14 10:08:53 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622412085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3622412085
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/18.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all_with_rand_reset.17074237
Short name T171
Test name
Test status
Simulation time 5597312842 ps
CPU time 18.99 seconds
Started Oct 14 10:09:11 PM UTC 24
Finished Oct 14 10:09:31 PM UTC 24
Peak memory 209392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=17074237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 21.aon_timer_stress_all_with_rand_reset.17074237
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.3005427651
Short name T179
Test name
Test status
Simulation time 171741460257 ps
CPU time 320.71 seconds
Started Oct 14 10:09:28 PM UTC 24
Finished Oct 14 10:14:53 PM UTC 24
Peak memory 203416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005427651 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.3005427651
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/24.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all.1619371706
Short name T168
Test name
Test status
Simulation time 205529532153 ps
CPU time 181.17 seconds
Started Oct 14 10:10:10 PM UTC 24
Finished Oct 14 10:13:14 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619371706 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all.1619371706
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/29.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.426302723
Short name T111
Test name
Test status
Simulation time 226263650735 ps
CPU time 180.07 seconds
Started Oct 14 10:07:13 PM UTC 24
Finished Oct 14 10:10:16 PM UTC 24
Peak memory 203600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426302723 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.426302723
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all_with_rand_reset.4183769477
Short name T177
Test name
Test status
Simulation time 3717949376 ps
CPU time 11.42 seconds
Started Oct 14 10:11:39 PM UTC 24
Finished Oct 14 10:11:51 PM UTC 24
Peak memory 212600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4183769477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 44.aon_timer_stress_all_with_rand_reset.4183769477
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.478227672
Short name T89
Test name
Test status
Simulation time 466028324 ps
CPU time 2.19 seconds
Started Oct 14 10:12:04 PM UTC 24
Finished Oct 14 10:12:08 PM UTC 24
Peak memory 203236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478227672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.478227672
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/49.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all.982043678
Short name T118
Test name
Test status
Simulation time 291312162964 ps
CPU time 464.48 seconds
Started Oct 14 10:08:08 PM UTC 24
Finished Oct 14 10:15:57 PM UTC 24
Peak memory 203344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982043678 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all.982043678
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/11.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.3000630488
Short name T100
Test name
Test status
Simulation time 407758779 ps
CPU time 1.24 seconds
Started Oct 14 10:08:36 PM UTC 24
Finished Oct 14 10:08:38 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000630488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3000630488
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/15.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all.399085277
Short name T153
Test name
Test status
Simulation time 34515414370 ps
CPU time 78.85 seconds
Started Oct 14 10:09:35 PM UTC 24
Finished Oct 14 10:10:56 PM UTC 24
Peak memory 203604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399085277 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all.399085277
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/25.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.2649848461
Short name T128
Test name
Test status
Simulation time 178859276538 ps
CPU time 52.98 seconds
Started Oct 14 10:10:37 PM UTC 24
Finished Oct 14 10:11:31 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649848461 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.2649848461
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/33.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.1708418199
Short name T34
Test name
Test status
Simulation time 4156924881 ps
CPU time 40.53 seconds
Started Oct 14 10:07:17 PM UTC 24
Finished Oct 14 10:07:59 PM UTC 24
Peak memory 220168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1708418199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 4.aon_timer_stress_all_with_rand_reset.1708418199
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.2598102206
Short name T103
Test name
Test status
Simulation time 604980602 ps
CPU time 3.09 seconds
Started Oct 14 10:11:24 PM UTC 24
Finished Oct 14 10:11:29 PM UTC 24
Peak memory 203484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598102206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2598102206
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/41.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.288822480
Short name T169
Test name
Test status
Simulation time 136704116073 ps
CPU time 213.24 seconds
Started Oct 14 10:07:51 PM UTC 24
Finished Oct 14 10:11:27 PM UTC 24
Peak memory 203600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288822480 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.288822480
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/8.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all_with_rand_reset.336041315
Short name T154
Test name
Test status
Simulation time 3678165578 ps
CPU time 41.74 seconds
Started Oct 14 10:08:19 PM UTC 24
Finished Oct 14 10:09:03 PM UTC 24
Peak memory 203692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=336041315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 13.aon_timer_stress_all_with_rand_reset.336041315
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all_with_rand_reset.3279931245
Short name T81
Test name
Test status
Simulation time 2375354707 ps
CPU time 20.57 seconds
Started Oct 14 10:08:48 PM UTC 24
Finished Oct 14 10:09:10 PM UTC 24
Peak memory 217992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3279931245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 17.aon_timer_stress_all_with_rand_reset.3279931245
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.2308255915
Short name T108
Test name
Test status
Simulation time 529435721 ps
CPU time 1.35 seconds
Started Oct 14 10:09:03 PM UTC 24
Finished Oct 14 10:09:05 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308255915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2308255915
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/20.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all_with_rand_reset.1284640502
Short name T140
Test name
Test status
Simulation time 2255938260 ps
CPU time 6.1 seconds
Started Oct 14 10:10:01 PM UTC 24
Finished Oct 14 10:10:08 PM UTC 24
Peak memory 209104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1284640502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 27.aon_timer_stress_all_with_rand_reset.1284640502
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.1321801832
Short name T92
Test name
Test status
Simulation time 536514549 ps
CPU time 1.27 seconds
Started Oct 14 10:10:13 PM UTC 24
Finished Oct 14 10:10:15 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321801832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1321801832
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/30.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all.2196800400
Short name T141
Test name
Test status
Simulation time 43456570611 ps
CPU time 23.17 seconds
Started Oct 14 10:10:14 PM UTC 24
Finished Oct 14 10:10:38 PM UTC 24
Peak memory 203668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196800400 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all.2196800400
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/30.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.833923942
Short name T113
Test name
Test status
Simulation time 358646286 ps
CPU time 1.25 seconds
Started Oct 14 10:11:06 PM UTC 24
Finished Oct 14 10:11:09 PM UTC 24
Peak memory 201312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833923942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.833923942
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/38.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all_with_rand_reset.1638696623
Short name T129
Test name
Test status
Simulation time 2251998035 ps
CPU time 10.22 seconds
Started Oct 14 10:11:19 PM UTC 24
Finished Oct 14 10:11:31 PM UTC 24
Peak memory 218192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1638696623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 40.aon_timer_stress_all_with_rand_reset.1638696623
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.2111740771
Short name T101
Test name
Test status
Simulation time 409852943 ps
CPU time 1.65 seconds
Started Oct 14 10:11:32 PM UTC 24
Finished Oct 14 10:11:35 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111740771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2111740771
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/42.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all_with_rand_reset.3176456064
Short name T160
Test name
Test status
Simulation time 2437055999 ps
CPU time 21.81 seconds
Started Oct 14 10:11:43 PM UTC 24
Finished Oct 14 10:12:06 PM UTC 24
Peak memory 220300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3176456064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 45.aon_timer_stress_all_with_rand_reset.3176456064
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.1117110002
Short name T30
Test name
Test status
Simulation time 573747327 ps
CPU time 1.38 seconds
Started Oct 14 10:07:41 PM UTC 24
Finished Oct 14 10:07:43 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117110002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1117110002
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/7.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.2180159868
Short name T159
Test name
Test status
Simulation time 467415573 ps
CPU time 1.28 seconds
Started Oct 14 10:08:41 PM UTC 24
Finished Oct 14 10:08:44 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180159868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2180159868
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/16.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.354692939
Short name T80
Test name
Test status
Simulation time 2665270931 ps
CPU time 7.73 seconds
Started Oct 14 10:08:41 PM UTC 24
Finished Oct 14 10:08:50 PM UTC 24
Peak memory 203648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=354692939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 16.aon_timer_stress_all_with_rand_reset.354692939
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all_with_rand_reset.2927352359
Short name T82
Test name
Test status
Simulation time 5298444174 ps
CPU time 15.93 seconds
Started Oct 14 10:09:00 PM UTC 24
Finished Oct 14 10:09:17 PM UTC 24
Peak memory 212600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2927352359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 19.aon_timer_stress_all_with_rand_reset.2927352359
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.2048938279
Short name T10
Test name
Test status
Simulation time 458729593 ps
CPU time 1.62 seconds
Started Oct 14 10:07:10 PM UTC 24
Finished Oct 14 10:07:13 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048938279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2048938279
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.2380990099
Short name T146
Test name
Test status
Simulation time 389117633 ps
CPU time 2.28 seconds
Started Oct 14 10:10:39 PM UTC 24
Finished Oct 14 10:10:42 PM UTC 24
Peak memory 203152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380990099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2380990099
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/34.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.3378849975
Short name T87
Test name
Test status
Simulation time 632024244 ps
CPU time 1.09 seconds
Started Oct 14 10:11:54 PM UTC 24
Finished Oct 14 10:11:56 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378849975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3378849975
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/47.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.425548853
Short name T22
Test name
Test status
Simulation time 468065766 ps
CPU time 1.99 seconds
Started Oct 14 10:07:19 PM UTC 24
Finished Oct 14 10:07:22 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425548853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.425548853
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/5.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.3926573277
Short name T119
Test name
Test status
Simulation time 456891122 ps
CPU time 2.6 seconds
Started Oct 14 10:09:19 PM UTC 24
Finished Oct 14 10:09:23 PM UTC 24
Peak memory 203484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926573277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3926573277
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/23.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.4117196747
Short name T130
Test name
Test status
Simulation time 487916610 ps
CPU time 1.52 seconds
Started Oct 14 10:09:32 PM UTC 24
Finished Oct 14 10:09:34 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117196747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.4117196747
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/25.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.4154232984
Short name T133
Test name
Test status
Simulation time 505760301 ps
CPU time 1.56 seconds
Started Oct 14 10:09:44 PM UTC 24
Finished Oct 14 10:09:47 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154232984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.4154232984
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/26.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.800312832
Short name T173
Test name
Test status
Simulation time 207846086849 ps
CPU time 159.81 seconds
Started Oct 14 10:07:18 PM UTC 24
Finished Oct 14 10:10:00 PM UTC 24
Peak memory 203108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800312832 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.800312832
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.2632700941
Short name T86
Test name
Test status
Simulation time 358823210 ps
CPU time 2.19 seconds
Started Oct 14 10:11:15 PM UTC 24
Finished Oct 14 10:11:18 PM UTC 24
Peak memory 203156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632700941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2632700941
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/40.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.2087203857
Short name T148
Test name
Test status
Simulation time 364979582 ps
CPU time 2.09 seconds
Started Oct 14 10:11:42 PM UTC 24
Finished Oct 14 10:11:45 PM UTC 24
Peak memory 203164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087203857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2087203857
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/45.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.3494626044
Short name T165
Test name
Test status
Simulation time 52351151915 ps
CPU time 91.87 seconds
Started Oct 14 10:11:57 PM UTC 24
Finished Oct 14 10:13:31 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494626044 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.3494626044
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/47.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all_with_rand_reset.1023116091
Short name T121
Test name
Test status
Simulation time 1476055746 ps
CPU time 13.87 seconds
Started Oct 14 10:12:01 PM UTC 24
Finished Oct 14 10:12:16 PM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1023116091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 48.aon_timer_stress_all_with_rand_reset.1023116091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.393532373
Short name T137
Test name
Test status
Simulation time 562866001 ps
CPU time 1.28 seconds
Started Oct 14 10:09:26 PM UTC 24
Finished Oct 14 10:09:28 PM UTC 24
Peak memory 201312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393532373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.393532373
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/24.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.3473054583
Short name T145
Test name
Test status
Simulation time 559470095 ps
CPU time 1.7 seconds
Started Oct 14 10:10:04 PM UTC 24
Finished Oct 14 10:10:07 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473054583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3473054583
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/28.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all.2017540185
Short name T180
Test name
Test status
Simulation time 138095284563 ps
CPU time 75.89 seconds
Started Oct 14 10:11:08 PM UTC 24
Finished Oct 14 10:12:26 PM UTC 24
Peak memory 203672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017540185 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.2017540185
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/38.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all_with_rand_reset.3451415223
Short name T190
Test name
Test status
Simulation time 3491400280 ps
CPU time 36.15 seconds
Started Oct 14 10:11:33 PM UTC 24
Finished Oct 14 10:12:11 PM UTC 24
Peak memory 221076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3451415223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 42.aon_timer_stress_all_with_rand_reset.3451415223
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all_with_rand_reset.3601832555
Short name T139
Test name
Test status
Simulation time 3874431505 ps
CPU time 29.54 seconds
Started Oct 14 10:12:08 PM UTC 24
Finished Oct 14 10:12:38 PM UTC 24
Peak memory 209356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3601832555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 49.aon_timer_stress_all_with_rand_reset.3601832555
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.2639602923
Short name T188
Test name
Test status
Simulation time 556534431 ps
CPU time 1.31 seconds
Started Oct 14 10:08:07 PM UTC 24
Finished Oct 14 10:08:09 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639602923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2639602923
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/11.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all_with_rand_reset.1975273786
Short name T157
Test name
Test status
Simulation time 4571869616 ps
CPU time 45.62 seconds
Started Oct 14 10:08:37 PM UTC 24
Finished Oct 14 10:09:24 PM UTC 24
Peak memory 217852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1975273786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 15.aon_timer_stress_all_with_rand_reset.1975273786
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.166215394
Short name T184
Test name
Test status
Simulation time 576110502 ps
CPU time 1.4 seconds
Started Oct 14 10:10:07 PM UTC 24
Finished Oct 14 10:10:10 PM UTC 24
Peak memory 201312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166215394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.166215394
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/29.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all_with_rand_reset.3053340096
Short name T20
Test name
Test status
Simulation time 2359674051 ps
CPU time 23.15 seconds
Started Oct 14 10:07:12 PM UTC 24
Finished Oct 14 10:07:37 PM UTC 24
Peak memory 219280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3053340096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 3.aon_timer_stress_all_with_rand_reset.3053340096
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.3484601494
Short name T164
Test name
Test status
Simulation time 521938625 ps
CPU time 1.01 seconds
Started Oct 14 10:10:19 PM UTC 24
Finished Oct 14 10:10:21 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484601494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3484601494
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/31.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.3027892018
Short name T186
Test name
Test status
Simulation time 550979086 ps
CPU time 1.16 seconds
Started Oct 14 10:10:25 PM UTC 24
Finished Oct 14 10:10:28 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027892018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3027892018
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/32.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.4109287078
Short name T183
Test name
Test status
Simulation time 427831197 ps
CPU time 2.39 seconds
Started Oct 14 10:10:53 PM UTC 24
Finished Oct 14 10:10:57 PM UTC 24
Peak memory 203152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109287078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.4109287078
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/35.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.3552580011
Short name T135
Test name
Test status
Simulation time 451999884 ps
CPU time 1.56 seconds
Started Oct 14 10:11:01 PM UTC 24
Finished Oct 14 10:11:04 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552580011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3552580011
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/37.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.1464486062
Short name T191
Test name
Test status
Simulation time 562760491 ps
CPU time 2.85 seconds
Started Oct 14 10:11:10 PM UTC 24
Finished Oct 14 10:11:14 PM UTC 24
Peak memory 203484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464486062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1464486062
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/39.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.1064871804
Short name T106
Test name
Test status
Simulation time 419496957 ps
CPU time 0.99 seconds
Started Oct 14 10:11:35 PM UTC 24
Finished Oct 14 10:11:37 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064871804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1064871804
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/43.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.2470626884
Short name T185
Test name
Test status
Simulation time 544716876 ps
CPU time 1.61 seconds
Started Oct 14 10:11:39 PM UTC 24
Finished Oct 14 10:11:41 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470626884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2470626884
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/44.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.1171451039
Short name T19
Test name
Test status
Simulation time 412246329 ps
CPU time 1.31 seconds
Started Oct 14 10:07:27 PM UTC 24
Finished Oct 14 10:07:30 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171451039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1171451039
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/6.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.4131065222
Short name T47
Test name
Test status
Simulation time 4042041208 ps
CPU time 30.28 seconds
Started Oct 14 10:07:58 PM UTC 24
Finished Oct 14 10:08:30 PM UTC 24
Peak memory 221224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4131065222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 9.aon_timer_stress_all_with_rand_reset.4131065222
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1284772944
Short name T357
Test name
Test status
Simulation time 4550826684 ps
CPU time 1.46 seconds
Started Oct 14 08:56:12 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284772944 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.1284772944
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.3188116342
Short name T46
Test name
Test status
Simulation time 2425205908 ps
CPU time 11.18 seconds
Started Oct 14 10:08:02 PM UTC 24
Finished Oct 14 10:08:15 PM UTC 24
Peak memory 209384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3188116342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 10.aon_timer_stress_all_with_rand_reset.3188116342
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all_with_rand_reset.2376284028
Short name T78
Test name
Test status
Simulation time 2550487104 ps
CPU time 21.33 seconds
Started Oct 14 10:08:08 PM UTC 24
Finished Oct 14 10:08:30 PM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2376284028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 11.aon_timer_stress_all_with_rand_reset.2376284028
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.3541092223
Short name T52
Test name
Test status
Simulation time 552155672 ps
CPU time 2.9 seconds
Started Oct 14 10:08:13 PM UTC 24
Finished Oct 14 10:08:17 PM UTC 24
Peak memory 203548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541092223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3541092223
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/12.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.2595169288
Short name T166
Test name
Test status
Simulation time 578321337 ps
CPU time 1.03 seconds
Started Oct 14 10:08:18 PM UTC 24
Finished Oct 14 10:08:20 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595169288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2595169288
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/13.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.2332137890
Short name T174
Test name
Test status
Simulation time 563578622 ps
CPU time 1.65 seconds
Started Oct 14 10:08:47 PM UTC 24
Finished Oct 14 10:08:49 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332137890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2332137890
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/17.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.3647235680
Short name T189
Test name
Test status
Simulation time 587166537 ps
CPU time 2.69 seconds
Started Oct 14 10:08:59 PM UTC 24
Finished Oct 14 10:09:02 PM UTC 24
Peak memory 203484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647235680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3647235680
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/19.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.635053658
Short name T192
Test name
Test status
Simulation time 140734430955 ps
CPU time 85.01 seconds
Started Oct 14 10:09:03 PM UTC 24
Finished Oct 14 10:10:30 PM UTC 24
Peak memory 203268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635053658 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.635053658
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/20.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.1001432291
Short name T178
Test name
Test status
Simulation time 440413472 ps
CPU time 2.43 seconds
Started Oct 14 10:09:14 PM UTC 24
Finished Oct 14 10:09:17 PM UTC 24
Peak memory 203156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001432291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1001432291
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/22.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.4002941625
Short name T199
Test name
Test status
Simulation time 448187729 ps
CPU time 2.41 seconds
Started Oct 14 10:09:58 PM UTC 24
Finished Oct 14 10:10:01 PM UTC 24
Peak memory 203152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002941625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.4002941625
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/27.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.1246452617
Short name T181
Test name
Test status
Simulation time 619712519 ps
CPU time 1.3 seconds
Started Oct 14 10:10:32 PM UTC 24
Finished Oct 14 10:10:34 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246452617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1246452617
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/33.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.4090015874
Short name T193
Test name
Test status
Simulation time 512936749 ps
CPU time 1.48 seconds
Started Oct 14 10:10:57 PM UTC 24
Finished Oct 14 10:10:59 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090015874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.4090015874
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/36.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.1191200065
Short name T14
Test name
Test status
Simulation time 673203173 ps
CPU time 1.07 seconds
Started Oct 14 10:07:15 PM UTC 24
Finished Oct 14 10:07:17 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191200065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1191200065
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all_with_rand_reset.1733069112
Short name T194
Test name
Test status
Simulation time 9144215840 ps
CPU time 25.13 seconds
Started Oct 14 10:11:26 PM UTC 24
Finished Oct 14 10:11:53 PM UTC 24
Peak memory 209060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1733069112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 41.aon_timer_stress_all_with_rand_reset.1733069112
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2220352605
Short name T39
Test name
Test status
Simulation time 3959943591 ps
CPU time 6.03 seconds
Started Oct 14 08:55:45 PM UTC 24
Finished Oct 14 08:55:52 PM UTC 24
Peak memory 205872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220352605 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.2220352605
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1664384216
Short name T205
Test name
Test status
Simulation time 9861789494 ps
CPU time 2.32 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 206196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664384216 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.1664384216
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.4058313706
Short name T4
Test name
Test status
Simulation time 529580421 ps
CPU time 1.49 seconds
Started Oct 14 10:07:03 PM UTC 24
Finished Oct 14 10:07:05 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058313706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.4058313706
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.3955355742
Short name T6
Test name
Test status
Simulation time 510459139 ps
CPU time 2.68 seconds
Started Oct 14 10:07:03 PM UTC 24
Finished Oct 14 10:07:07 PM UTC 24
Peak memory 203484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955355742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3955355742
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.127746919
Short name T200
Test name
Test status
Simulation time 4697905354 ps
CPU time 13.84 seconds
Started Oct 14 10:09:21 PM UTC 24
Finished Oct 14 10:09:36 PM UTC 24
Peak memory 221408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=127746919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 23.aon_timer_stress_all_with_rand_reset.127746919
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.3126476502
Short name T84
Test name
Test status
Simulation time 4320557083 ps
CPU time 30.38 seconds
Started Oct 14 10:09:33 PM UTC 24
Finished Oct 14 10:10:05 PM UTC 24
Peak memory 222180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3126476502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 25.aon_timer_stress_all_with_rand_reset.3126476502
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all_with_rand_reset.342904725
Short name T197
Test name
Test status
Simulation time 9380318057 ps
CPU time 31.64 seconds
Started Oct 14 10:10:35 PM UTC 24
Finished Oct 14 10:11:08 PM UTC 24
Peak memory 220872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=342904725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 33.aon_timer_stress_all_with_rand_reset.342904725
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.568504805
Short name T175
Test name
Test status
Simulation time 566778201 ps
CPU time 1.08 seconds
Started Oct 14 10:11:50 PM UTC 24
Finished Oct 14 10:11:52 PM UTC 24
Peak memory 201312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568504805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.568504805
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/46.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all_with_rand_reset.2893088580
Short name T33
Test name
Test status
Simulation time 1096811543 ps
CPU time 5.05 seconds
Started Oct 14 10:07:51 PM UTC 24
Finished Oct 14 10:07:57 PM UTC 24
Peak memory 220020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2893088580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 8.aon_timer_stress_all_with_rand_reset.2893088580
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4227413997
Short name T56
Test name
Test status
Simulation time 14087276844 ps
CPU time 9.68 seconds
Started Oct 14 08:55:45 PM UTC 24
Finished Oct 14 08:55:56 PM UTC 24
Peak memory 201084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227413997 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.4227413997
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.471241671
Short name T36
Test name
Test status
Simulation time 739612861 ps
CPU time 0.92 seconds
Started Oct 14 08:55:45 PM UTC 24
Finished Oct 14 08:55:47 PM UTC 24
Peak memory 199352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471241671 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.471241671
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3325070491
Short name T216
Test name
Test status
Simulation time 317328664 ps
CPU time 0.79 seconds
Started Oct 14 08:55:48 PM UTC 24
Finished Oct 14 08:55:50 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3325070491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim
er_csr_mem_rw_with_rand_reset.3325070491
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.3287609736
Short name T292
Test name
Test status
Simulation time 511126766 ps
CPU time 0.59 seconds
Started Oct 14 08:55:45 PM UTC 24
Finished Oct 14 08:55:47 PM UTC 24
Peak memory 200284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287609736 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3287609736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.964797553
Short name T294
Test name
Test status
Simulation time 279049272 ps
CPU time 0.82 seconds
Started Oct 14 08:55:45 PM UTC 24
Finished Oct 14 08:55:47 PM UTC 24
Peak memory 199688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964797553 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.964797553
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.3567454319
Short name T293
Test name
Test status
Simulation time 331227060 ps
CPU time 0.71 seconds
Started Oct 14 08:55:45 PM UTC 24
Finished Oct 14 08:55:47 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567454319 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.3567454319
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3781097930
Short name T38
Test name
Test status
Simulation time 1360790701 ps
CPU time 1.39 seconds
Started Oct 14 08:55:48 PM UTC 24
Finished Oct 14 08:55:51 PM UTC 24
Peak memory 199756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781097930 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.3781097930
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.408867186
Short name T295
Test name
Test status
Simulation time 377202632 ps
CPU time 2.24 seconds
Started Oct 14 08:55:45 PM UTC 24
Finished Oct 14 08:55:49 PM UTC 24
Peak memory 201280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408867186 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.408867186
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2211785188
Short name T54
Test name
Test status
Simulation time 375372339 ps
CPU time 0.7 seconds
Started Oct 14 08:55:53 PM UTC 24
Finished Oct 14 08:55:54 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211785188 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.2211785188
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.75420486
Short name T55
Test name
Test status
Simulation time 5554836284 ps
CPU time 1.83 seconds
Started Oct 14 08:55:53 PM UTC 24
Finished Oct 14 08:55:55 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75420486 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.75420486
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2857980471
Short name T43
Test name
Test status
Simulation time 725880759 ps
CPU time 0.61 seconds
Started Oct 14 08:55:50 PM UTC 24
Finished Oct 14 08:55:51 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857980471 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.2857980471
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.957878359
Short name T301
Test name
Test status
Simulation time 318572616 ps
CPU time 0.98 seconds
Started Oct 14 08:55:53 PM UTC 24
Finished Oct 14 08:55:55 PM UTC 24
Peak memory 199740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=957878359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_time
r_csr_mem_rw_with_rand_reset.957878359
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.3306081696
Short name T76
Test name
Test status
Simulation time 404841707 ps
CPU time 0.99 seconds
Started Oct 14 08:55:52 PM UTC 24
Finished Oct 14 08:55:54 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306081696 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3306081696
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.1008769872
Short name T298
Test name
Test status
Simulation time 302995451 ps
CPU time 0.89 seconds
Started Oct 14 08:55:49 PM UTC 24
Finished Oct 14 08:55:51 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008769872 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1008769872
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1012848064
Short name T299
Test name
Test status
Simulation time 472551456 ps
CPU time 1.08 seconds
Started Oct 14 08:55:50 PM UTC 24
Finished Oct 14 08:55:52 PM UTC 24
Peak memory 199752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012848064 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.1012848064
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.4085551171
Short name T297
Test name
Test status
Simulation time 402585390 ps
CPU time 0.68 seconds
Started Oct 14 08:55:49 PM UTC 24
Finished Oct 14 08:55:51 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085551171 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.4085551171
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2652171678
Short name T70
Test name
Test status
Simulation time 1128556453 ps
CPU time 1.29 seconds
Started Oct 14 08:55:53 PM UTC 24
Finished Oct 14 08:55:55 PM UTC 24
Peak memory 199756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652171678 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.2652171678
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.3020373292
Short name T296
Test name
Test status
Simulation time 666267657 ps
CPU time 1.74 seconds
Started Oct 14 08:55:48 PM UTC 24
Finished Oct 14 08:55:51 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020373292 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3020373292
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.730892849
Short name T345
Test name
Test status
Simulation time 416125014 ps
CPU time 1.19 seconds
Started Oct 14 08:56:12 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=730892849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_tim
er_csr_mem_rw_with_rand_reset.730892849
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.3893566533
Short name T341
Test name
Test status
Simulation time 396209423 ps
CPU time 0.58 seconds
Started Oct 14 08:56:12 PM UTC 24
Finished Oct 14 08:56:14 PM UTC 24
Peak memory 197692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893566533 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3893566533
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.3255613899
Short name T340
Test name
Test status
Simulation time 502584541 ps
CPU time 0.53 seconds
Started Oct 14 08:56:12 PM UTC 24
Finished Oct 14 08:56:14 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255613899 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3255613899
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/10.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1511559187
Short name T353
Test name
Test status
Simulation time 2329196757 ps
CPU time 1.42 seconds
Started Oct 14 08:56:12 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511559187 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.1511559187
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.2454324385
Short name T378
Test name
Test status
Simulation time 972179435 ps
CPU time 2.38 seconds
Started Oct 14 08:56:12 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 201352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454324385 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2454324385
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3794081244
Short name T374
Test name
Test status
Simulation time 4287990053 ps
CPU time 2.27 seconds
Started Oct 14 08:56:12 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 205912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794081244 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.3794081244
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1208122487
Short name T354
Test name
Test status
Simulation time 315477939 ps
CPU time 1.12 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1208122487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_ti
mer_csr_mem_rw_with_rand_reset.1208122487
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.3978256220
Short name T65
Test name
Test status
Simulation time 337821647 ps
CPU time 0.88 seconds
Started Oct 14 08:56:12 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978256220 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3978256220
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.2657712194
Short name T342
Test name
Test status
Simulation time 318165369 ps
CPU time 0.7 seconds
Started Oct 14 08:56:12 PM UTC 24
Finished Oct 14 08:56:14 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657712194 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2657712194
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/11.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.353437951
Short name T397
Test name
Test status
Simulation time 2861977825 ps
CPU time 4.07 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:18 PM UTC 24
Peak memory 200936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353437951 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.353437951
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.3905310740
Short name T360
Test name
Test status
Simulation time 569177502 ps
CPU time 1.61 seconds
Started Oct 14 08:56:12 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905310740 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3905310740
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.463221789
Short name T347
Test name
Test status
Simulation time 372336007 ps
CPU time 0.65 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=463221789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_tim
er_csr_mem_rw_with_rand_reset.463221789
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.47286200
Short name T350
Test name
Test status
Simulation time 331831337 ps
CPU time 0.93 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47286200 -assert nopostproc +UVM_TESTNAME=aon_
timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.47286200
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.26465940
Short name T355
Test name
Test status
Simulation time 359594043 ps
CPU time 1.05 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26465940 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.26465940
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/12.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.243634600
Short name T379
Test name
Test status
Simulation time 2490584842 ps
CPU time 1.7 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 199752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243634600 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.243634600
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.3148050934
Short name T363
Test name
Test status
Simulation time 426205560 ps
CPU time 1.48 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148050934 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3148050934
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2119177160
Short name T406
Test name
Test status
Simulation time 3844999269 ps
CPU time 6.14 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:20 PM UTC 24
Peak memory 206548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119177160 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.2119177160
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1454872266
Short name T356
Test name
Test status
Simulation time 444156261 ps
CPU time 0.75 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1454872266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_ti
mer_csr_mem_rw_with_rand_reset.1454872266
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.1832228843
Short name T66
Test name
Test status
Simulation time 351801321 ps
CPU time 0.68 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832228843 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1832228843
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.1133516780
Short name T366
Test name
Test status
Simulation time 470171688 ps
CPU time 1.26 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133516780 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1133516780
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/13.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2100800006
Short name T387
Test name
Test status
Simulation time 1472097071 ps
CPU time 2.01 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 201008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100800006 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.2100800006
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3127069284
Short name T382
Test name
Test status
Simulation time 500248966 ps
CPU time 1.73 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127069284 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3127069284
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3753593247
Short name T370
Test name
Test status
Simulation time 475978201 ps
CPU time 0.95 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3753593247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_ti
mer_csr_mem_rw_with_rand_reset.3753593247
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.2778677905
Short name T358
Test name
Test status
Simulation time 356205781 ps
CPU time 0.63 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778677905 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2778677905
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.2907442587
Short name T372
Test name
Test status
Simulation time 394734726 ps
CPU time 1.28 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907442587 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2907442587
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/14.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2955800427
Short name T390
Test name
Test status
Simulation time 1482952713 ps
CPU time 2.25 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:17 PM UTC 24
Peak memory 200944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955800427 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.2955800427
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.800501674
Short name T386
Test name
Test status
Simulation time 571788318 ps
CPU time 1.98 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800501674 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.800501674
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2922967031
Short name T367
Test name
Test status
Simulation time 4398371603 ps
CPU time 7.21 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:22 PM UTC 24
Peak memory 201012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922967031 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.2922967031
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1714453917
Short name T362
Test name
Test status
Simulation time 464698136 ps
CPU time 0.78 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1714453917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_ti
mer_csr_mem_rw_with_rand_reset.1714453917
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.323880753
Short name T369
Test name
Test status
Simulation time 280898952 ps
CPU time 0.94 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323880753 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.323880753
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.4218938758
Short name T371
Test name
Test status
Simulation time 372302122 ps
CPU time 1.05 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218938758 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.4218938758
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/15.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1478890406
Short name T401
Test name
Test status
Simulation time 2511212477 ps
CPU time 3.8 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:18 PM UTC 24
Peak memory 201200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478890406 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.1478890406
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.1879050934
Short name T375
Test name
Test status
Simulation time 455891102 ps
CPU time 1.25 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879050934 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1879050934
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.355025047
Short name T207
Test name
Test status
Simulation time 4016253441 ps
CPU time 2.26 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:17 PM UTC 24
Peak memory 205036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355025047 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.355025047
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.241689288
Short name T373
Test name
Test status
Simulation time 318517677 ps
CPU time 0.84 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 199676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=241689288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_tim
er_csr_mem_rw_with_rand_reset.241689288
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.1271878119
Short name T364
Test name
Test status
Simulation time 443751537 ps
CPU time 0.65 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271878119 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1271878119
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.3453711274
Short name T365
Test name
Test status
Simulation time 403876828 ps
CPU time 0.72 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453711274 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3453711274
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/16.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.799474014
Short name T388
Test name
Test status
Simulation time 2086655321 ps
CPU time 1.8 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:17 PM UTC 24
Peak memory 199640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799474014 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.799474014
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.2908101309
Short name T377
Test name
Test status
Simulation time 351916212 ps
CPU time 1.16 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908101309 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2908101309
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.310995906
Short name T394
Test name
Test status
Simulation time 4439034602 ps
CPU time 2.39 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:17 PM UTC 24
Peak memory 205656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310995906 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.310995906
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3082646580
Short name T380
Test name
Test status
Simulation time 536418673 ps
CPU time 0.94 seconds
Started Oct 14 08:56:14 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 199672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3082646580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_ti
mer_csr_mem_rw_with_rand_reset.3082646580
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.762748505
Short name T67
Test name
Test status
Simulation time 420848537 ps
CPU time 0.65 seconds
Started Oct 14 08:56:14 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762748505 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.762748505
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.3590189722
Short name T383
Test name
Test status
Simulation time 365289248 ps
CPU time 1.12 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590189722 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3590189722
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/17.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1869216742
Short name T381
Test name
Test status
Simulation time 1370023004 ps
CPU time 0.95 seconds
Started Oct 14 08:56:14 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 199688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869216742 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.1869216742
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.94232483
Short name T391
Test name
Test status
Simulation time 542735182 ps
CPU time 1.88 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:17 PM UTC 24
Peak memory 205436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94232483 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.94232483
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1791858708
Short name T206
Test name
Test status
Simulation time 8717752616 ps
CPU time 3.55 seconds
Started Oct 14 08:56:13 PM UTC 24
Finished Oct 14 08:56:18 PM UTC 24
Peak memory 201236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791858708 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.1791858708
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1824369916
Short name T392
Test name
Test status
Simulation time 398614383 ps
CPU time 0.92 seconds
Started Oct 14 08:56:15 PM UTC 24
Finished Oct 14 08:56:17 PM UTC 24
Peak memory 199672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1824369916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_ti
mer_csr_mem_rw_with_rand_reset.1824369916
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.2124921458
Short name T376
Test name
Test status
Simulation time 338776050 ps
CPU time 0.66 seconds
Started Oct 14 08:56:14 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 199616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124921458 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2124921458
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.919670763
Short name T384
Test name
Test status
Simulation time 410506376 ps
CPU time 1.07 seconds
Started Oct 14 08:56:14 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919670763 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.919670763
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/18.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2187567662
Short name T396
Test name
Test status
Simulation time 2248452091 ps
CPU time 2.74 seconds
Started Oct 14 08:56:14 PM UTC 24
Finished Oct 14 08:56:18 PM UTC 24
Peak memory 201140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187567662 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.2187567662
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.3023395122
Short name T385
Test name
Test status
Simulation time 531206301 ps
CPU time 1.19 seconds
Started Oct 14 08:56:14 PM UTC 24
Finished Oct 14 08:56:16 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023395122 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3023395122
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2081818308
Short name T404
Test name
Test status
Simulation time 8617024205 ps
CPU time 4.06 seconds
Started Oct 14 08:56:14 PM UTC 24
Finished Oct 14 08:56:19 PM UTC 24
Peak memory 206736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081818308 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.2081818308
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1852501796
Short name T393
Test name
Test status
Simulation time 366676941 ps
CPU time 0.78 seconds
Started Oct 14 08:56:15 PM UTC 24
Finished Oct 14 08:56:17 PM UTC 24
Peak memory 199672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1852501796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_ti
mer_csr_mem_rw_with_rand_reset.1852501796
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.172167506
Short name T68
Test name
Test status
Simulation time 529965769 ps
CPU time 0.97 seconds
Started Oct 14 08:56:15 PM UTC 24
Finished Oct 14 08:56:17 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172167506 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.172167506
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.2619244787
Short name T389
Test name
Test status
Simulation time 484662325 ps
CPU time 0.69 seconds
Started Oct 14 08:56:15 PM UTC 24
Finished Oct 14 08:56:17 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619244787 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2619244787
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/19.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4222068890
Short name T405
Test name
Test status
Simulation time 2404881427 ps
CPU time 3.49 seconds
Started Oct 14 08:56:15 PM UTC 24
Finished Oct 14 08:56:20 PM UTC 24
Peak memory 200936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222068890 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.4222068890
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.2161845769
Short name T402
Test name
Test status
Simulation time 530828562 ps
CPU time 2.57 seconds
Started Oct 14 08:56:15 PM UTC 24
Finished Oct 14 08:56:18 PM UTC 24
Peak memory 201472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161845769 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2161845769
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1111744910
Short name T361
Test name
Test status
Simulation time 8529479623 ps
CPU time 10.19 seconds
Started Oct 14 08:56:15 PM UTC 24
Finished Oct 14 08:56:26 PM UTC 24
Peak memory 201208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111744910 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.1111744910
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3566411060
Short name T305
Test name
Test status
Simulation time 603035304 ps
CPU time 0.77 seconds
Started Oct 14 08:55:55 PM UTC 24
Finished Oct 14 08:55:57 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566411060 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.3566411060
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2664543510
Short name T336
Test name
Test status
Simulation time 7018797145 ps
CPU time 13.35 seconds
Started Oct 14 08:55:55 PM UTC 24
Finished Oct 14 08:56:09 PM UTC 24
Peak memory 201412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664543510 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.2664543510
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.645922293
Short name T77
Test name
Test status
Simulation time 852706082 ps
CPU time 0.6 seconds
Started Oct 14 08:55:54 PM UTC 24
Finished Oct 14 08:55:56 PM UTC 24
Peak memory 199684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645922293 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.645922293
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.70484204
Short name T307
Test name
Test status
Simulation time 297608102 ps
CPU time 0.83 seconds
Started Oct 14 08:55:56 PM UTC 24
Finished Oct 14 08:55:58 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=70484204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer
_csr_mem_rw_with_rand_reset.70484204
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.4055236253
Short name T57
Test name
Test status
Simulation time 389711701 ps
CPU time 0.96 seconds
Started Oct 14 08:55:55 PM UTC 24
Finished Oct 14 08:55:57 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055236253 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.4055236253
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.1898565192
Short name T300
Test name
Test status
Simulation time 279699458 ps
CPU time 0.73 seconds
Started Oct 14 08:55:53 PM UTC 24
Finished Oct 14 08:55:55 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898565192 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1898565192
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3350487983
Short name T304
Test name
Test status
Simulation time 523340563 ps
CPU time 0.88 seconds
Started Oct 14 08:55:54 PM UTC 24
Finished Oct 14 08:55:56 PM UTC 24
Peak memory 199752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350487983 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.3350487983
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.1754934862
Short name T302
Test name
Test status
Simulation time 288405417 ps
CPU time 0.83 seconds
Started Oct 14 08:55:53 PM UTC 24
Finished Oct 14 08:55:55 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754934862 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.1754934862
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.409679737
Short name T71
Test name
Test status
Simulation time 1148161366 ps
CPU time 2.06 seconds
Started Oct 14 08:55:55 PM UTC 24
Finished Oct 14 08:55:58 PM UTC 24
Peak memory 201008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409679737 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.409679737
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.3518049435
Short name T303
Test name
Test status
Simulation time 350339882 ps
CPU time 1.69 seconds
Started Oct 14 08:55:53 PM UTC 24
Finished Oct 14 08:55:56 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518049435 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3518049435
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3501027353
Short name T41
Test name
Test status
Simulation time 4002956240 ps
CPU time 5.96 seconds
Started Oct 14 08:55:53 PM UTC 24
Finished Oct 14 08:56:00 PM UTC 24
Peak memory 206180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501027353 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.3501027353
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.2326064024
Short name T395
Test name
Test status
Simulation time 476568440 ps
CPU time 1.16 seconds
Started Oct 14 08:56:15 PM UTC 24
Finished Oct 14 08:56:17 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326064024 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2326064024
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/20.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.2845540416
Short name T398
Test name
Test status
Simulation time 317188485 ps
CPU time 0.74 seconds
Started Oct 14 08:56:16 PM UTC 24
Finished Oct 14 08:56:18 PM UTC 24
Peak memory 199532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845540416 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2845540416
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/21.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.108877884
Short name T399
Test name
Test status
Simulation time 500031747 ps
CPU time 0.8 seconds
Started Oct 14 08:56:16 PM UTC 24
Finished Oct 14 08:56:18 PM UTC 24
Peak memory 199520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108877884 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.108877884
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/22.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.4189492976
Short name T400
Test name
Test status
Simulation time 313177081 ps
CPU time 0.92 seconds
Started Oct 14 08:56:16 PM UTC 24
Finished Oct 14 08:56:18 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189492976 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.4189492976
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/23.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.3563059116
Short name T403
Test name
Test status
Simulation time 490442275 ps
CPU time 1.26 seconds
Started Oct 14 08:56:16 PM UTC 24
Finished Oct 14 08:56:19 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563059116 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3563059116
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/24.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.334357104
Short name T352
Test name
Test status
Simulation time 316585786 ps
CPU time 0.91 seconds
Started Oct 14 08:56:16 PM UTC 24
Finished Oct 14 08:56:31 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334357104 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.334357104
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/25.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.3291885372
Short name T349
Test name
Test status
Simulation time 321274677 ps
CPU time 0.97 seconds
Started Oct 14 08:56:16 PM UTC 24
Finished Oct 14 08:56:31 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291885372 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3291885372
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/26.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.1306232852
Short name T351
Test name
Test status
Simulation time 424246482 ps
CPU time 0.71 seconds
Started Oct 14 08:56:16 PM UTC 24
Finished Oct 14 08:56:31 PM UTC 24
Peak memory 198640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306232852 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1306232852
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/27.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.3111439188
Short name T359
Test name
Test status
Simulation time 275704613 ps
CPU time 0.84 seconds
Started Oct 14 08:56:16 PM UTC 24
Finished Oct 14 08:56:31 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111439188 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3111439188
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/28.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.1122346226
Short name T408
Test name
Test status
Simulation time 407664520 ps
CPU time 1.03 seconds
Started Oct 14 08:56:16 PM UTC 24
Finished Oct 14 08:56:32 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122346226 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1122346226
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/29.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2564020531
Short name T311
Test name
Test status
Simulation time 460860170 ps
CPU time 0.68 seconds
Started Oct 14 08:55:58 PM UTC 24
Finished Oct 14 08:56:00 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564020531 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.2564020531
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.209629734
Short name T64
Test name
Test status
Simulation time 5623803847 ps
CPU time 11.95 seconds
Started Oct 14 08:55:58 PM UTC 24
Finished Oct 14 08:56:12 PM UTC 24
Peak memory 201428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209629734 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.209629734
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2556634451
Short name T312
Test name
Test status
Simulation time 1057245441 ps
CPU time 1.91 seconds
Started Oct 14 08:55:57 PM UTC 24
Finished Oct 14 08:56:00 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556634451 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.2556634451
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1961622821
Short name T313
Test name
Test status
Simulation time 451431458 ps
CPU time 1.13 seconds
Started Oct 14 08:55:59 PM UTC 24
Finished Oct 14 08:56:02 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1961622821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_tim
er_csr_mem_rw_with_rand_reset.1961622821
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.42195551
Short name T72
Test name
Test status
Simulation time 470934716 ps
CPU time 1.14 seconds
Started Oct 14 08:55:57 PM UTC 24
Finished Oct 14 08:56:00 PM UTC 24
Peak memory 198120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42195551 -assert nopostproc +UVM_TESTNAME=aon_
timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.42195551
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.2956251530
Short name T306
Test name
Test status
Simulation time 427091609 ps
CPU time 0.63 seconds
Started Oct 14 08:55:56 PM UTC 24
Finished Oct 14 08:55:58 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956251530 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2956251530
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1417081705
Short name T310
Test name
Test status
Simulation time 461665354 ps
CPU time 0.58 seconds
Started Oct 14 08:55:57 PM UTC 24
Finished Oct 14 08:55:59 PM UTC 24
Peak memory 198416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417081705 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.1417081705
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.1698706725
Short name T308
Test name
Test status
Simulation time 496822959 ps
CPU time 1.05 seconds
Started Oct 14 08:55:56 PM UTC 24
Finished Oct 14 08:55:58 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698706725 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.1698706725
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2510262511
Short name T73
Test name
Test status
Simulation time 1821814213 ps
CPU time 1.19 seconds
Started Oct 14 08:55:59 PM UTC 24
Finished Oct 14 08:56:02 PM UTC 24
Peak memory 199752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510262511 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.2510262511
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.94222984
Short name T309
Test name
Test status
Simulation time 519045676 ps
CPU time 1.8 seconds
Started Oct 14 08:55:56 PM UTC 24
Finished Oct 14 08:55:59 PM UTC 24
Peak memory 199664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94222984 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.94222984
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3281218956
Short name T201
Test name
Test status
Simulation time 8141593510 ps
CPU time 7.08 seconds
Started Oct 14 08:55:56 PM UTC 24
Finished Oct 14 08:56:04 PM UTC 24
Peak memory 201236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281218956 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.3281218956
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.346776124
Short name T368
Test name
Test status
Simulation time 509375584 ps
CPU time 0.85 seconds
Started Oct 14 08:56:16 PM UTC 24
Finished Oct 14 08:56:32 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346776124 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.346776124
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/30.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.723043573
Short name T407
Test name
Test status
Simulation time 338151151 ps
CPU time 0.61 seconds
Started Oct 14 08:56:16 PM UTC 24
Finished Oct 14 08:56:31 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723043573 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.723043573
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/31.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.3393795976
Short name T410
Test name
Test status
Simulation time 459568663 ps
CPU time 1.06 seconds
Started Oct 14 08:56:16 PM UTC 24
Finished Oct 14 08:56:32 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393795976 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3393795976
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/32.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2712463396
Short name T409
Test name
Test status
Simulation time 498058338 ps
CPU time 1.14 seconds
Started Oct 14 08:56:16 PM UTC 24
Finished Oct 14 08:56:32 PM UTC 24
Peak memory 198888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712463396 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2712463396
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/33.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3640885169
Short name T58
Test name
Test status
Simulation time 474622652 ps
CPU time 1.02 seconds
Started Oct 14 08:56:03 PM UTC 24
Finished Oct 14 08:56:05 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640885169 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.3640885169
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3836042549
Short name T61
Test name
Test status
Simulation time 1053725413 ps
CPU time 1.68 seconds
Started Oct 14 08:56:03 PM UTC 24
Finished Oct 14 08:56:06 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836042549 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.3836042549
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2662771776
Short name T316
Test name
Test status
Simulation time 1255029011 ps
CPU time 0.8 seconds
Started Oct 14 08:56:01 PM UTC 24
Finished Oct 14 08:56:02 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662771776 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.2662771776
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3833469135
Short name T319
Test name
Test status
Simulation time 509857260 ps
CPU time 0.93 seconds
Started Oct 14 08:56:03 PM UTC 24
Finished Oct 14 08:56:05 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3833469135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_tim
er_csr_mem_rw_with_rand_reset.3833469135
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.3202840092
Short name T59
Test name
Test status
Simulation time 467623171 ps
CPU time 1.2 seconds
Started Oct 14 08:56:03 PM UTC 24
Finished Oct 14 08:56:05 PM UTC 24
Peak memory 201668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202840092 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3202840092
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.1407609619
Short name T318
Test name
Test status
Simulation time 470674613 ps
CPU time 1.13 seconds
Started Oct 14 08:56:01 PM UTC 24
Finished Oct 14 08:56:03 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407609619 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1407609619
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.380656659
Short name T315
Test name
Test status
Simulation time 376500198 ps
CPU time 0.6 seconds
Started Oct 14 08:56:01 PM UTC 24
Finished Oct 14 08:56:02 PM UTC 24
Peak memory 199692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380656659 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.380656659
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.1693447817
Short name T317
Test name
Test status
Simulation time 310463944 ps
CPU time 0.9 seconds
Started Oct 14 08:56:01 PM UTC 24
Finished Oct 14 08:56:03 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693447817 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.1693447817
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1479956866
Short name T74
Test name
Test status
Simulation time 1411804744 ps
CPU time 0.7 seconds
Started Oct 14 08:56:03 PM UTC 24
Finished Oct 14 08:56:05 PM UTC 24
Peak memory 199756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479956866 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.1479956866
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.1038222464
Short name T314
Test name
Test status
Simulation time 1171144822 ps
CPU time 1.41 seconds
Started Oct 14 08:56:00 PM UTC 24
Finished Oct 14 08:56:02 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038222464 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1038222464
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3409642218
Short name T202
Test name
Test status
Simulation time 8409473911 ps
CPU time 4.09 seconds
Started Oct 14 08:56:00 PM UTC 24
Finished Oct 14 08:56:05 PM UTC 24
Peak memory 206064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409642218 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.3409642218
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.3936210332
Short name T413
Test name
Test status
Simulation time 362456209 ps
CPU time 0.99 seconds
Started Oct 14 08:56:17 PM UTC 24
Finished Oct 14 08:56:42 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936210332 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3936210332
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/42.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.2734495297
Short name T414
Test name
Test status
Simulation time 314713082 ps
CPU time 1.02 seconds
Started Oct 14 08:56:17 PM UTC 24
Finished Oct 14 08:56:42 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734495297 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2734495297
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/43.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.4245019094
Short name T412
Test name
Test status
Simulation time 482147070 ps
CPU time 0.61 seconds
Started Oct 14 08:56:17 PM UTC 24
Finished Oct 14 08:56:42 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245019094 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.4245019094
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/44.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.3667034630
Short name T411
Test name
Test status
Simulation time 433171738 ps
CPU time 0.57 seconds
Started Oct 14 08:56:17 PM UTC 24
Finished Oct 14 08:56:42 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667034630 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3667034630
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/45.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.1659115632
Short name T415
Test name
Test status
Simulation time 440415910 ps
CPU time 1.26 seconds
Started Oct 14 08:56:17 PM UTC 24
Finished Oct 14 08:56:42 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659115632 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1659115632
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/46.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.2128631316
Short name T416
Test name
Test status
Simulation time 368634845 ps
CPU time 1.72 seconds
Started Oct 14 08:56:17 PM UTC 24
Finished Oct 14 08:56:50 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128631316 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2128631316
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/47.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3602504986
Short name T324
Test name
Test status
Simulation time 416148703 ps
CPU time 0.91 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:07 PM UTC 24
Peak memory 203832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3602504986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_tim
er_csr_mem_rw_with_rand_reset.3602504986
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.312622296
Short name T60
Test name
Test status
Simulation time 496727473 ps
CPU time 0.89 seconds
Started Oct 14 08:56:03 PM UTC 24
Finished Oct 14 08:56:05 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312622296 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.312622296
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.2366648352
Short name T320
Test name
Test status
Simulation time 345496881 ps
CPU time 0.92 seconds
Started Oct 14 08:56:03 PM UTC 24
Finished Oct 14 08:56:05 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366648352 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2366648352
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/5.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2221163176
Short name T335
Test name
Test status
Simulation time 2043263756 ps
CPU time 2.74 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:09 PM UTC 24
Peak memory 200876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221163176 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.2221163176
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.2063656221
Short name T321
Test name
Test status
Simulation time 473980746 ps
CPU time 1.65 seconds
Started Oct 14 08:56:03 PM UTC 24
Finished Oct 14 08:56:06 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063656221 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2063656221
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1523613778
Short name T322
Test name
Test status
Simulation time 4599773232 ps
CPU time 2.21 seconds
Started Oct 14 08:56:03 PM UTC 24
Finished Oct 14 08:56:06 PM UTC 24
Peak memory 205116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523613778 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.1523613778
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2806438342
Short name T327
Test name
Test status
Simulation time 475147983 ps
CPU time 1.14 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:07 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2806438342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_tim
er_csr_mem_rw_with_rand_reset.2806438342
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.3883214000
Short name T62
Test name
Test status
Simulation time 543499369 ps
CPU time 1.27 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:07 PM UTC 24
Peak memory 201668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883214000 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3883214000
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.3257609835
Short name T325
Test name
Test status
Simulation time 360927110 ps
CPU time 0.94 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:07 PM UTC 24
Peak memory 199592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257609835 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3257609835
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/6.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3386271104
Short name T75
Test name
Test status
Simulation time 999573219 ps
CPU time 0.9 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:07 PM UTC 24
Peak memory 199756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386271104 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.3386271104
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.1464977599
Short name T329
Test name
Test status
Simulation time 499506041 ps
CPU time 1.52 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:08 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464977599 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1464977599
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2625724964
Short name T338
Test name
Test status
Simulation time 3954237110 ps
CPU time 5.98 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:12 PM UTC 24
Peak memory 201248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625724964 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.2625724964
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1892858132
Short name T328
Test name
Test status
Simulation time 465877525 ps
CPU time 0.98 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:07 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1892858132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_tim
er_csr_mem_rw_with_rand_reset.1892858132
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.4247380448
Short name T63
Test name
Test status
Simulation time 374659937 ps
CPU time 0.92 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:07 PM UTC 24
Peak memory 198596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247380448 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.4247380448
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.1362168915
Short name T323
Test name
Test status
Simulation time 403139054 ps
CPU time 0.67 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:07 PM UTC 24
Peak memory 198444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362168915 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1362168915
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/7.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3616123585
Short name T337
Test name
Test status
Simulation time 2677735336 ps
CPU time 3.65 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:10 PM UTC 24
Peak memory 201012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616123585 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.3616123585
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.3477564141
Short name T330
Test name
Test status
Simulation time 941285816 ps
CPU time 1.65 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:08 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477564141 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3477564141
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1535415529
Short name T204
Test name
Test status
Simulation time 4638760507 ps
CPU time 5.67 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:12 PM UTC 24
Peak memory 206524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535415529 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.1535415529
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3888886628
Short name T331
Test name
Test status
Simulation time 533409669 ps
CPU time 1.39 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:08 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3888886628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_tim
er_csr_mem_rw_with_rand_reset.3888886628
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.64448027
Short name T69
Test name
Test status
Simulation time 304833761 ps
CPU time 0.72 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:07 PM UTC 24
Peak memory 199136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64448027 -assert nopostproc +UVM_TESTNAME=aon_
timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.64448027
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.1873704001
Short name T326
Test name
Test status
Simulation time 316626551 ps
CPU time 0.72 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:07 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873704001 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1873704001
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/8.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3571338727
Short name T332
Test name
Test status
Simulation time 1534039360 ps
CPU time 1.41 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:08 PM UTC 24
Peak memory 199756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571338727 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.3571338727
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.964175474
Short name T334
Test name
Test status
Simulation time 362958654 ps
CPU time 2.32 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:09 PM UTC 24
Peak memory 200952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964175474 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.964175474
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1140416707
Short name T203
Test name
Test status
Simulation time 4462798431 ps
CPU time 5.9 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:12 PM UTC 24
Peak memory 200944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140416707 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.1140416707
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1721798981
Short name T346
Test name
Test status
Simulation time 494106067 ps
CPU time 1.34 seconds
Started Oct 14 08:56:12 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1721798981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_tim
er_csr_mem_rw_with_rand_reset.1721798981
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.2434096651
Short name T339
Test name
Test status
Simulation time 411166169 ps
CPU time 0.64 seconds
Started Oct 14 08:56:12 PM UTC 24
Finished Oct 14 08:56:14 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434096651 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2434096651
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.456575388
Short name T343
Test name
Test status
Simulation time 492996844 ps
CPU time 1.2 seconds
Started Oct 14 08:56:12 PM UTC 24
Finished Oct 14 08:56:14 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456575388 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.456575388
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/9.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.805365062
Short name T344
Test name
Test status
Simulation time 2248157726 ps
CPU time 1.37 seconds
Started Oct 14 08:56:12 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 199752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805365062 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.805365062
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.1676498676
Short name T333
Test name
Test status
Simulation time 527601336 ps
CPU time 1.93 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:09 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676498676 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1676498676
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2877459104
Short name T348
Test name
Test status
Simulation time 8491699120 ps
CPU time 8.13 seconds
Started Oct 14 08:56:05 PM UTC 24
Finished Oct 14 08:56:15 PM UTC 24
Peak memory 206200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877459104 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.2877459104
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.869168902
Short name T211
Test name
Test status
Simulation time 24170756554 ps
CPU time 75.86 seconds
Started Oct 14 10:07:01 PM UTC 24
Finished Oct 14 10:08:19 PM UTC 24
Peak memory 203272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869168902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.869168902
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.2598690114
Short name T2
Test name
Test status
Simulation time 568935827 ps
CPU time 2.69 seconds
Started Oct 14 10:07:01 PM UTC 24
Finished Oct 14 10:07:05 PM UTC 24
Peak memory 203540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598690114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2598690114
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/0.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.4025370455
Short name T8
Test name
Test status
Simulation time 8007769240 ps
CPU time 6.71 seconds
Started Oct 14 10:07:03 PM UTC 24
Finished Oct 14 10:07:11 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025370455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.4025370455
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.3082271656
Short name T12
Test name
Test status
Simulation time 4865503279 ps
CPU time 3.16 seconds
Started Oct 14 10:07:04 PM UTC 24
Finished Oct 14 10:07:09 PM UTC 24
Peak memory 233964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082271656 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3082271656
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.2369424502
Short name T3
Test name
Test status
Simulation time 399470780 ps
CPU time 1.18 seconds
Started Oct 14 10:07:03 PM UTC 24
Finished Oct 14 10:07:05 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369424502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2369424502
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/1.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.4159219859
Short name T51
Test name
Test status
Simulation time 617981551 ps
CPU time 1.28 seconds
Started Oct 14 10:08:00 PM UTC 24
Finished Oct 14 10:08:02 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159219859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.4159219859
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/10.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.4243483652
Short name T221
Test name
Test status
Simulation time 34563763645 ps
CPU time 19.83 seconds
Started Oct 14 10:08:00 PM UTC 24
Finished Oct 14 10:08:21 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243483652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.4243483652
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/10.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.3681369556
Short name T217
Test name
Test status
Simulation time 430473431 ps
CPU time 2.4 seconds
Started Oct 14 10:07:59 PM UTC 24
Finished Oct 14 10:08:02 PM UTC 24
Peak memory 203084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681369556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3681369556
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/10.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.780199629
Short name T213
Test name
Test status
Simulation time 43929175421 ps
CPU time 65.87 seconds
Started Oct 14 10:08:05 PM UTC 24
Finished Oct 14 10:09:13 PM UTC 24
Peak memory 203608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780199629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.780199629
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/11.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.2655326033
Short name T218
Test name
Test status
Simulation time 533525104 ps
CPU time 2.34 seconds
Started Oct 14 10:08:03 PM UTC 24
Finished Oct 14 10:08:07 PM UTC 24
Peak memory 203148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655326033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2655326033
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/11.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.1862201116
Short name T212
Test name
Test status
Simulation time 20300161348 ps
CPU time 32.04 seconds
Started Oct 14 10:08:13 PM UTC 24
Finished Oct 14 10:08:46 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862201116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1862201116
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/12.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.3148568798
Short name T162
Test name
Test status
Simulation time 455737851 ps
CPU time 1.24 seconds
Started Oct 14 10:08:10 PM UTC 24
Finished Oct 14 10:08:12 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148568798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3148568798
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/12.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.2161932894
Short name T53
Test name
Test status
Simulation time 26848315920 ps
CPU time 16.92 seconds
Started Oct 14 10:08:18 PM UTC 24
Finished Oct 14 10:08:36 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161932894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2161932894
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/13.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.1587013931
Short name T220
Test name
Test status
Simulation time 457828936 ps
CPU time 0.96 seconds
Started Oct 14 10:08:15 PM UTC 24
Finished Oct 14 10:08:17 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587013931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1587013931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/13.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.3144437315
Short name T228
Test name
Test status
Simulation time 58384629900 ps
CPU time 26.36 seconds
Started Oct 14 10:08:26 PM UTC 24
Finished Oct 14 10:08:53 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144437315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3144437315
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/14.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.1097345014
Short name T222
Test name
Test status
Simulation time 505502274 ps
CPU time 1.83 seconds
Started Oct 14 10:08:21 PM UTC 24
Finished Oct 14 10:08:24 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097345014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1097345014
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/14.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.3915979030
Short name T232
Test name
Test status
Simulation time 40144840842 ps
CPU time 33.15 seconds
Started Oct 14 10:08:35 PM UTC 24
Finished Oct 14 10:09:09 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915979030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3915979030
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/15.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.3896424638
Short name T163
Test name
Test status
Simulation time 436023136 ps
CPU time 0.87 seconds
Started Oct 14 10:08:32 PM UTC 24
Finished Oct 14 10:08:34 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896424638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3896424638
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/15.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.1516162671
Short name T214
Test name
Test status
Simulation time 36968283129 ps
CPU time 31.69 seconds
Started Oct 14 10:08:40 PM UTC 24
Finished Oct 14 10:09:13 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516162671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1516162671
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/16.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.325693286
Short name T225
Test name
Test status
Simulation time 387418189 ps
CPU time 1.2 seconds
Started Oct 14 10:08:40 PM UTC 24
Finished Oct 14 10:08:42 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325693286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.325693286
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/16.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.358487137
Short name T249
Test name
Test status
Simulation time 38663775622 ps
CPU time 91.55 seconds
Started Oct 14 10:08:47 PM UTC 24
Finished Oct 14 10:10:20 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358487137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.358487137
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/17.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.4084496017
Short name T226
Test name
Test status
Simulation time 482125994 ps
CPU time 0.95 seconds
Started Oct 14 10:08:45 PM UTC 24
Finished Oct 14 10:08:47 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084496017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.4084496017
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/17.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.197530944
Short name T208
Test name
Test status
Simulation time 989536650 ps
CPU time 1.63 seconds
Started Oct 14 10:08:51 PM UTC 24
Finished Oct 14 10:08:54 PM UTC 24
Peak memory 202096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197530944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.197530944
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/18.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.2817566787
Short name T227
Test name
Test status
Simulation time 416560939 ps
CPU time 1.04 seconds
Started Oct 14 10:08:50 PM UTC 24
Finished Oct 14 10:08:52 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817566787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2817566787
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/18.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.2730132770
Short name T272
Test name
Test status
Simulation time 61748642407 ps
CPU time 156.23 seconds
Started Oct 14 10:08:54 PM UTC 24
Finished Oct 14 10:11:33 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730132770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2730132770
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/19.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.1176769283
Short name T229
Test name
Test status
Simulation time 588336140 ps
CPU time 3.06 seconds
Started Oct 14 10:08:54 PM UTC 24
Finished Oct 14 10:08:58 PM UTC 24
Peak memory 202764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176769283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1176769283
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/19.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.1545544325
Short name T48
Test name
Test status
Simulation time 44984260196 ps
CPU time 36.59 seconds
Started Oct 14 10:07:06 PM UTC 24
Finished Oct 14 10:07:44 PM UTC 24
Peak memory 203672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545544325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1545544325
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.3008009685
Short name T24
Test name
Test status
Simulation time 7844354869 ps
CPU time 8.02 seconds
Started Oct 14 10:07:08 PM UTC 24
Finished Oct 14 10:07:17 PM UTC 24
Peak memory 234100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008009685 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3008009685
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.1867123047
Short name T5
Test name
Test status
Simulation time 503724246 ps
CPU time 1.22 seconds
Started Oct 14 10:07:05 PM UTC 24
Finished Oct 14 10:07:07 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867123047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1867123047
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/2.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.275232202
Short name T262
Test name
Test status
Simulation time 40806406266 ps
CPU time 117.19 seconds
Started Oct 14 10:09:01 PM UTC 24
Finished Oct 14 10:11:00 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275232202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.275232202
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/20.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.833495602
Short name T230
Test name
Test status
Simulation time 392242799 ps
CPU time 1.48 seconds
Started Oct 14 10:09:00 PM UTC 24
Finished Oct 14 10:09:02 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833495602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.833495602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/20.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all_with_rand_reset.1662408336
Short name T83
Test name
Test status
Simulation time 2059343378 ps
CPU time 18.2 seconds
Started Oct 14 10:09:03 PM UTC 24
Finished Oct 14 10:09:22 PM UTC 24
Peak memory 217376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1662408336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 20.aon_timer_stress_all_with_rand_reset.1662408336
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.971145994
Short name T195
Test name
Test status
Simulation time 409081924 ps
CPU time 1.04 seconds
Started Oct 14 10:09:09 PM UTC 24
Finished Oct 14 10:09:11 PM UTC 24
Peak memory 201312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971145994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.971145994
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/21.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.12674142
Short name T210
Test name
Test status
Simulation time 14631930883 ps
CPU time 22.34 seconds
Started Oct 14 10:09:08 PM UTC 24
Finished Oct 14 10:09:32 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12674142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.12674142
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/21.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.3495803673
Short name T231
Test name
Test status
Simulation time 381902387 ps
CPU time 1.35 seconds
Started Oct 14 10:09:06 PM UTC 24
Finished Oct 14 10:09:09 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495803673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3495803673
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/21.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.547350415
Short name T251
Test name
Test status
Simulation time 23300266780 ps
CPU time 68.87 seconds
Started Oct 14 10:09:13 PM UTC 24
Finished Oct 14 10:10:23 PM UTC 24
Peak memory 203672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547350415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.547350415
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/22.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.3302216650
Short name T233
Test name
Test status
Simulation time 366314295 ps
CPU time 1.43 seconds
Started Oct 14 10:09:13 PM UTC 24
Finished Oct 14 10:09:15 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302216650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3302216650
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/22.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.977383897
Short name T240
Test name
Test status
Simulation time 60572588756 ps
CPU time 40.46 seconds
Started Oct 14 10:09:18 PM UTC 24
Finished Oct 14 10:10:00 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977383897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.977383897
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/23.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.3355656306
Short name T234
Test name
Test status
Simulation time 576616776 ps
CPU time 1.24 seconds
Started Oct 14 10:09:18 PM UTC 24
Finished Oct 14 10:09:20 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355656306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3355656306
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/23.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.533600525
Short name T243
Test name
Test status
Simulation time 21809980133 ps
CPU time 40.03 seconds
Started Oct 14 10:09:24 PM UTC 24
Finished Oct 14 10:10:06 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533600525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.533600525
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/24.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.803302887
Short name T235
Test name
Test status
Simulation time 636909633 ps
CPU time 1.24 seconds
Started Oct 14 10:09:23 PM UTC 24
Finished Oct 14 10:09:26 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803302887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.803302887
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/24.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.3530057876
Short name T246
Test name
Test status
Simulation time 47282916468 ps
CPU time 38.5 seconds
Started Oct 14 10:09:32 PM UTC 24
Finished Oct 14 10:10:12 PM UTC 24
Peak memory 203416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530057876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3530057876
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/25.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.4238098192
Short name T236
Test name
Test status
Simulation time 416426873 ps
CPU time 0.91 seconds
Started Oct 14 10:09:29 PM UTC 24
Finished Oct 14 10:09:31 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238098192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.4238098192
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/25.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.1094118736
Short name T209
Test name
Test status
Simulation time 12259446475 ps
CPU time 19.19 seconds
Started Oct 14 10:09:41 PM UTC 24
Finished Oct 14 10:10:02 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094118736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1094118736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/26.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.2637987046
Short name T237
Test name
Test status
Simulation time 388220394 ps
CPU time 2.35 seconds
Started Oct 14 10:09:37 PM UTC 24
Finished Oct 14 10:09:40 PM UTC 24
Peak memory 203540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637987046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2637987046
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/26.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.2816462618
Short name T241
Test name
Test status
Simulation time 33904452304 ps
CPU time 10.32 seconds
Started Oct 14 10:09:53 PM UTC 24
Finished Oct 14 10:10:05 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816462618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2816462618
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/27.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.2247973883
Short name T239
Test name
Test status
Simulation time 495957517 ps
CPU time 2.14 seconds
Started Oct 14 10:09:53 PM UTC 24
Finished Oct 14 10:09:57 PM UTC 24
Peak memory 203148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247973883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2247973883
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/27.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.412088744
Short name T245
Test name
Test status
Simulation time 3594393241 ps
CPU time 7.04 seconds
Started Oct 14 10:10:03 PM UTC 24
Finished Oct 14 10:10:11 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412088744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.412088744
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/28.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.3924507186
Short name T242
Test name
Test status
Simulation time 542233619 ps
CPU time 1.3 seconds
Started Oct 14 10:10:03 PM UTC 24
Finished Oct 14 10:10:05 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924507186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3924507186
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/28.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.3128249969
Short name T253
Test name
Test status
Simulation time 22787117594 ps
CPU time 17.49 seconds
Started Oct 14 10:10:07 PM UTC 24
Finished Oct 14 10:10:26 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128249969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3128249969
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/29.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.3866384314
Short name T244
Test name
Test status
Simulation time 616292757 ps
CPU time 1.67 seconds
Started Oct 14 10:10:06 PM UTC 24
Finished Oct 14 10:10:09 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866384314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3866384314
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/29.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all_with_rand_reset.3761504365
Short name T196
Test name
Test status
Simulation time 8766380604 ps
CPU time 25.72 seconds
Started Oct 14 10:10:09 PM UTC 24
Finished Oct 14 10:10:36 PM UTC 24
Peak memory 222108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3761504365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 29.aon_timer_stress_all_with_rand_reset.3761504365
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.3550478029
Short name T13
Test name
Test status
Simulation time 3226108426 ps
CPU time 2.54 seconds
Started Oct 14 10:07:10 PM UTC 24
Finished Oct 14 10:07:14 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550478029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3550478029
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.4003442507
Short name T27
Test name
Test status
Simulation time 4091862632 ps
CPU time 3.61 seconds
Started Oct 14 10:07:13 PM UTC 24
Finished Oct 14 10:07:18 PM UTC 24
Peak memory 233604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003442507 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.4003442507
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.790404769
Short name T9
Test name
Test status
Simulation time 354892922 ps
CPU time 2.21 seconds
Started Oct 14 10:07:09 PM UTC 24
Finished Oct 14 10:07:12 PM UTC 24
Peak memory 203228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790404769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.790404769
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/3.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.219018782
Short name T250
Test name
Test status
Simulation time 8161725084 ps
CPU time 8.35 seconds
Started Oct 14 10:10:13 PM UTC 24
Finished Oct 14 10:10:22 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219018782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.219018782
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/30.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.1905316627
Short name T247
Test name
Test status
Simulation time 495731154 ps
CPU time 1.1 seconds
Started Oct 14 10:10:10 PM UTC 24
Finished Oct 14 10:10:12 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905316627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1905316627
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/30.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.4043276341
Short name T252
Test name
Test status
Simulation time 3595957140 ps
CPU time 6.22 seconds
Started Oct 14 10:10:17 PM UTC 24
Finished Oct 14 10:10:24 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043276341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.4043276341
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/31.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.3069047142
Short name T248
Test name
Test status
Simulation time 360357732 ps
CPU time 1.19 seconds
Started Oct 14 10:10:16 PM UTC 24
Finished Oct 14 10:10:18 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069047142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3069047142
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/31.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.2381063034
Short name T259
Test name
Test status
Simulation time 48751921570 ps
CPU time 27.12 seconds
Started Oct 14 10:10:24 PM UTC 24
Finished Oct 14 10:10:53 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381063034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2381063034
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/32.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.4293708014
Short name T254
Test name
Test status
Simulation time 356644360 ps
CPU time 2 seconds
Started Oct 14 10:10:23 PM UTC 24
Finished Oct 14 10:10:26 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293708014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.4293708014
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/32.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.3049038258
Short name T265
Test name
Test status
Simulation time 26737381278 ps
CPU time 34.04 seconds
Started Oct 14 10:10:31 PM UTC 24
Finished Oct 14 10:11:06 PM UTC 24
Peak memory 203672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049038258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3049038258
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/33.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.1830896576
Short name T255
Test name
Test status
Simulation time 479404015 ps
CPU time 1.16 seconds
Started Oct 14 10:10:28 PM UTC 24
Finished Oct 14 10:10:31 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830896576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1830896576
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/33.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.3690443462
Short name T258
Test name
Test status
Simulation time 37000046425 ps
CPU time 12.25 seconds
Started Oct 14 10:10:39 PM UTC 24
Finished Oct 14 10:10:52 PM UTC 24
Peak memory 203608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690443462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3690443462
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/34.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.3267586244
Short name T256
Test name
Test status
Simulation time 638505962 ps
CPU time 1.41 seconds
Started Oct 14 10:10:37 PM UTC 24
Finished Oct 14 10:10:39 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267586244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3267586244
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/34.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.3981438462
Short name T260
Test name
Test status
Simulation time 5117354867 ps
CPU time 4.67 seconds
Started Oct 14 10:10:47 PM UTC 24
Finished Oct 14 10:10:53 PM UTC 24
Peak memory 203608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981438462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3981438462
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/35.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.2475855077
Short name T257
Test name
Test status
Simulation time 417811561 ps
CPU time 2.35 seconds
Started Oct 14 10:10:43 PM UTC 24
Finished Oct 14 10:10:47 PM UTC 24
Peak memory 203476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475855077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2475855077
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/35.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.577149477
Short name T264
Test name
Test status
Simulation time 13342423539 ps
CPU time 10.01 seconds
Started Oct 14 10:10:55 PM UTC 24
Finished Oct 14 10:11:06 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577149477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.577149477
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/36.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.2973714308
Short name T261
Test name
Test status
Simulation time 492481089 ps
CPU time 1.29 seconds
Started Oct 14 10:10:55 PM UTC 24
Finished Oct 14 10:10:57 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973714308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2973714308
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/36.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.1694294802
Short name T276
Test name
Test status
Simulation time 26310808827 ps
CPU time 35.25 seconds
Started Oct 14 10:11:00 PM UTC 24
Finished Oct 14 10:11:37 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694294802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1694294802
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/37.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.263557810
Short name T263
Test name
Test status
Simulation time 537045052 ps
CPU time 1.92 seconds
Started Oct 14 10:10:58 PM UTC 24
Finished Oct 14 10:11:01 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263557810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.263557810
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/37.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.3301980510
Short name T273
Test name
Test status
Simulation time 35500863403 ps
CPU time 28.03 seconds
Started Oct 14 10:11:04 PM UTC 24
Finished Oct 14 10:11:34 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301980510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3301980510
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/38.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.1743974420
Short name T266
Test name
Test status
Simulation time 458479517 ps
CPU time 2.54 seconds
Started Oct 14 10:11:03 PM UTC 24
Finished Oct 14 10:11:07 PM UTC 24
Peak memory 203476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743974420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1743974420
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/38.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.2754581424
Short name T271
Test name
Test status
Simulation time 5451270981 ps
CPU time 21.79 seconds
Started Oct 14 10:11:10 PM UTC 24
Finished Oct 14 10:11:33 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754581424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2754581424
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/39.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.3996806686
Short name T267
Test name
Test status
Simulation time 503541517 ps
CPU time 1.33 seconds
Started Oct 14 10:11:09 PM UTC 24
Finished Oct 14 10:11:11 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996806686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3996806686
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/39.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.2036890734
Short name T215
Test name
Test status
Simulation time 950321726 ps
CPU time 6.51 seconds
Started Oct 14 10:11:12 PM UTC 24
Finished Oct 14 10:11:19 PM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2036890734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 39.aon_timer_stress_all_with_rand_reset.2036890734
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.2097793514
Short name T16
Test name
Test status
Simulation time 5370704324 ps
CPU time 2.67 seconds
Started Oct 14 10:07:13 PM UTC 24
Finished Oct 14 10:07:17 PM UTC 24
Peak memory 203260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097793514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2097793514
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.1060025664
Short name T28
Test name
Test status
Simulation time 4354802811 ps
CPU time 4.16 seconds
Started Oct 14 10:07:18 PM UTC 24
Finished Oct 14 10:07:23 PM UTC 24
Peak memory 233892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060025664 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1060025664
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.2235353454
Short name T15
Test name
Test status
Simulation time 407040658 ps
CPU time 2.17 seconds
Started Oct 14 10:07:13 PM UTC 24
Finished Oct 14 10:07:17 PM UTC 24
Peak memory 202956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235353454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2235353454
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/4.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.2995341013
Short name T288
Test name
Test status
Simulation time 29362017715 ps
CPU time 62.6 seconds
Started Oct 14 10:11:14 PM UTC 24
Finished Oct 14 10:12:18 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995341013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2995341013
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/40.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.3809525429
Short name T268
Test name
Test status
Simulation time 567644899 ps
CPU time 1.25 seconds
Started Oct 14 10:11:12 PM UTC 24
Finished Oct 14 10:11:14 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809525429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3809525429
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/40.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.2316433150
Short name T274
Test name
Test status
Simulation time 12882023401 ps
CPU time 10.71 seconds
Started Oct 14 10:11:22 PM UTC 24
Finished Oct 14 10:11:34 PM UTC 24
Peak memory 203672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316433150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2316433150
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/41.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.3786331329
Short name T269
Test name
Test status
Simulation time 573511159 ps
CPU time 1.57 seconds
Started Oct 14 10:11:20 PM UTC 24
Finished Oct 14 10:11:23 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786331329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3786331329
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/41.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.395916239
Short name T281
Test name
Test status
Simulation time 14720634058 ps
CPU time 24.92 seconds
Started Oct 14 10:11:32 PM UTC 24
Finished Oct 14 10:11:58 PM UTC 24
Peak memory 203672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395916239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.395916239
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/42.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.1992312609
Short name T270
Test name
Test status
Simulation time 379600938 ps
CPU time 1.06 seconds
Started Oct 14 10:11:30 PM UTC 24
Finished Oct 14 10:11:32 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992312609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1992312609
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/42.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.3404353493
Short name T285
Test name
Test status
Simulation time 32285141886 ps
CPU time 28.53 seconds
Started Oct 14 10:11:34 PM UTC 24
Finished Oct 14 10:12:04 PM UTC 24
Peak memory 202220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404353493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3404353493
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/43.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.1477828286
Short name T275
Test name
Test status
Simulation time 360310013 ps
CPU time 1.3 seconds
Started Oct 14 10:11:34 PM UTC 24
Finished Oct 14 10:11:36 PM UTC 24
Peak memory 202360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477828286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1477828286
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/43.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.1309023539
Short name T291
Test name
Test status
Simulation time 61491011504 ps
CPU time 72.55 seconds
Started Oct 14 10:11:37 PM UTC 24
Finished Oct 14 10:12:52 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309023539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1309023539
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/44.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.1794324687
Short name T277
Test name
Test status
Simulation time 428309300 ps
CPU time 1.19 seconds
Started Oct 14 10:11:37 PM UTC 24
Finished Oct 14 10:11:40 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794324687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1794324687
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/44.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.1374811573
Short name T290
Test name
Test status
Simulation time 11545519862 ps
CPU time 42.4 seconds
Started Oct 14 10:11:41 PM UTC 24
Finished Oct 14 10:12:25 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374811573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1374811573
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/45.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.3901928504
Short name T278
Test name
Test status
Simulation time 528574276 ps
CPU time 1.15 seconds
Started Oct 14 10:11:40 PM UTC 24
Finished Oct 14 10:11:42 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901928504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3901928504
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/45.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.2695288509
Short name T283
Test name
Test status
Simulation time 5980080366 ps
CPU time 14.51 seconds
Started Oct 14 10:11:47 PM UTC 24
Finished Oct 14 10:12:03 PM UTC 24
Peak memory 203608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695288509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2695288509
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/46.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.2308908612
Short name T279
Test name
Test status
Simulation time 573278823 ps
CPU time 2.65 seconds
Started Oct 14 10:11:46 PM UTC 24
Finished Oct 14 10:11:50 PM UTC 24
Peak memory 203476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308908612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2308908612
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/46.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.1424361614
Short name T284
Test name
Test status
Simulation time 10308726849 ps
CPU time 8.63 seconds
Started Oct 14 10:11:54 PM UTC 24
Finished Oct 14 10:12:03 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424361614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1424361614
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/47.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.607946139
Short name T280
Test name
Test status
Simulation time 608077009 ps
CPU time 2.85 seconds
Started Oct 14 10:11:53 PM UTC 24
Finished Oct 14 10:11:57 PM UTC 24
Peak memory 203020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607946139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.607946139
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/47.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.446249483
Short name T187
Test name
Test status
Simulation time 481494461 ps
CPU time 0.97 seconds
Started Oct 14 10:12:01 PM UTC 24
Finished Oct 14 10:12:03 PM UTC 24
Peak memory 201312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446249483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.446249483
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/48.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.3422596742
Short name T287
Test name
Test status
Simulation time 14385921350 ps
CPU time 6.64 seconds
Started Oct 14 10:11:59 PM UTC 24
Finished Oct 14 10:12:07 PM UTC 24
Peak memory 203672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422596742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3422596742
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/48.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.2244768159
Short name T282
Test name
Test status
Simulation time 498147814 ps
CPU time 2.75 seconds
Started Oct 14 10:11:57 PM UTC 24
Finished Oct 14 10:12:01 PM UTC 24
Peak memory 203540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244768159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2244768159
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/48.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.2942102351
Short name T289
Test name
Test status
Simulation time 11127549096 ps
CPU time 18.53 seconds
Started Oct 14 10:12:04 PM UTC 24
Finished Oct 14 10:12:24 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942102351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2942102351
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/49.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.4066365156
Short name T286
Test name
Test status
Simulation time 448850191 ps
CPU time 0.99 seconds
Started Oct 14 10:12:04 PM UTC 24
Finished Oct 14 10:12:06 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066365156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.4066365156
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/49.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.2084576484
Short name T223
Test name
Test status
Simulation time 23177108908 ps
CPU time 70.65 seconds
Started Oct 14 10:07:18 PM UTC 24
Finished Oct 14 10:08:31 PM UTC 24
Peak memory 203284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084576484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2084576484
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/5.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.2716319814
Short name T21
Test name
Test status
Simulation time 429272321 ps
CPU time 1.67 seconds
Started Oct 14 10:07:18 PM UTC 24
Finished Oct 14 10:07:20 PM UTC 24
Peak memory 201124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716319814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2716319814
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/5.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.2407905260
Short name T224
Test name
Test status
Simulation time 44744312834 ps
CPU time 71.16 seconds
Started Oct 14 10:07:26 PM UTC 24
Finished Oct 14 10:08:39 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407905260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2407905260
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/6.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.3997708377
Short name T18
Test name
Test status
Simulation time 507163917 ps
CPU time 1.32 seconds
Started Oct 14 10:07:24 PM UTC 24
Finished Oct 14 10:07:27 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997708377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3997708377
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/6.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.153309351
Short name T49
Test name
Test status
Simulation time 5197564475 ps
CPU time 4.8 seconds
Started Oct 14 10:07:40 PM UTC 24
Finished Oct 14 10:07:46 PM UTC 24
Peak memory 203664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153309351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.153309351
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/7.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.1328488207
Short name T29
Test name
Test status
Simulation time 572182844 ps
CPU time 1.29 seconds
Started Oct 14 10:07:38 PM UTC 24
Finished Oct 14 10:07:40 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328488207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1328488207
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/7.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.1925937361
Short name T50
Test name
Test status
Simulation time 514980006 ps
CPU time 1.82 seconds
Started Oct 14 10:07:50 PM UTC 24
Finished Oct 14 10:07:53 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925937361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1925937361
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/8.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.2689538726
Short name T238
Test name
Test status
Simulation time 34312912982 ps
CPU time 112.17 seconds
Started Oct 14 10:07:49 PM UTC 24
Finished Oct 14 10:09:43 PM UTC 24
Peak memory 203288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689538726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2689538726
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/8.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.1535364196
Short name T31
Test name
Test status
Simulation time 551059235 ps
CPU time 1.08 seconds
Started Oct 14 10:07:46 PM UTC 24
Finished Oct 14 10:07:48 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535364196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1535364196
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/8.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.1490011816
Short name T198
Test name
Test status
Simulation time 574840438 ps
CPU time 1.38 seconds
Started Oct 14 10:07:57 PM UTC 24
Finished Oct 14 10:07:59 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490011816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1490011816
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/9.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.1112264629
Short name T219
Test name
Test status
Simulation time 11250241940 ps
CPU time 8.94 seconds
Started Oct 14 10:07:57 PM UTC 24
Finished Oct 14 10:08:07 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112264629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1112264629
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/9.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.2218155427
Short name T35
Test name
Test status
Simulation time 432404423 ps
CPU time 1.21 seconds
Started Oct 14 10:07:53 PM UTC 24
Finished Oct 14 10:07:56 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218155427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2218155427
Directory /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/9.aon_timer_smoke/latest
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