CLKMGR Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: 50278df8b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1341560578

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.510s	260.177us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.130s	158.786us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.020s	112.364us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	9.440s	1.430ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.620s	91.589us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.740s	82.595us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.020s	112.364us	20	20	100.00
		clkmgr_csr_aliasing	1.620s	91.589us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.010s	125.050us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.690s	246.684us	50	50	100.00
V2	extclk	clkmgr_extclk	1.400s	234.425us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.010s	141.831us	50	50	100.00
V2	jitter	clkmgr_smoke	1.510s	260.177us	50	50	100.00
V2	frequency	clkmgr_frequency	16.980s	2.480ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.210s	2.422ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	16.980s	2.480ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.381m	12.006ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.910s	108.374us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.310s	196.101us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.100s	726.357us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.100s	726.357us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.130s	158.786us	5	5	100.00
		clkmgr_csr_rw	1.020s	112.364us	20	20	100.00
		clkmgr_csr_aliasing	1.620s	91.589us	5	5	100.00
		clkmgr_same_csr_outstanding	2.130s	399.391us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.130s	158.786us	5	5	100.00
		clkmgr_csr_rw	1.020s	112.364us	20	20	100.00
		clkmgr_csr_aliasing	1.620s	91.589us	5	5	100.00
		clkmgr_same_csr_outstanding	2.130s	399.391us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	2.310s	356.427us	5	5	100.00
		clkmgr_tl_intg_err	4.780s	1.097ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.250s	454.785us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.250s	454.785us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.250s	454.785us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.250s	454.785us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	5.380s	1.011ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	4.780s	1.097ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	16.980s	2.480ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.210s	2.422ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.250s	454.785us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.870s	354.661us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.170s	152.155us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.180s	156.001us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.640s	294.430us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.410s	223.963us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.020s	112.364us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	2.310s	356.427us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.020s	112.364us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.020s	112.364us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	2.310s	356.427us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	31.865m	453.354ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			959	960	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	99.12	95.40	100.00	100.00	98.71	96.97	93.18

Failure Buckets

• Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)' has 1 failures:
  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 4.clkmgr_stress_all_with_rand_reset.1174991387
      Line 1093, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
        UVM_ERROR @ 23631299241 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
        UVM_INFO @ 23631299241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.15_18.30.36
• 2023.05.14_17.56.25
• 2023.05.13_18.39.16
• 2023.05.12_18.30.14
• 2023.05.12_11.14.02
• 2023.05.11_17.44.36
• 2023.05.11_10.32.14