7773b039d0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | clkmgr_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | clkmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | clkmgr_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | clkmgr_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | peri_enables | clkmgr_peri | 0 | 50 | 0.00 | ||
| V2 | trans_enables | clkmgr_trans | 0 | 50 | 0.00 | ||
| V2 | extclk | clkmgr_extclk | 0 | 50 | 0.00 | ||
| V2 | clk_status | clkmgr_clk_status | 0 | 50 | 0.00 | ||
| V2 | jitter | clkmgr_smoke | 0 | 50 | 0.00 | ||
| V2 | frequency | clkmgr_frequency | 0 | 50 | 0.00 | ||
| V2 | frequency_timeout | clkmgr_frequency_timeout | 0 | 50 | 0.00 | ||
| V2 | frequency_overflow | clkmgr_frequency | 0 | 50 | 0.00 | ||
| V2 | stress_all | clkmgr_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | clkmgr_intr_test | 0 | 50 | 0.00 | ||
| V2 | alert_test | clkmgr_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | clkmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | clkmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | clkmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| clkmgr_csr_rw | 0 | 20 | 0.00 | ||||
| clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| clkmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | clkmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| clkmgr_csr_rw | 0 | 20 | 0.00 | ||||
| clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| clkmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 490 | 0.00 | |||
| V2S | tl_intg_err | clkmgr_sec_cm | 0 | 5 | 0.00 | ||
| clkmgr_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | shadow_reg_update_error | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_read_clear_staged_value | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_storage_error | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadowed_reset_glitch | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_update_error_with_csr_rw | clkmgr_shadow_reg_errors_with_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_bus_integrity | clkmgr_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_meas_clk_bkgn_chk | clkmgr_frequency | 0 | 50 | 0.00 | ||
| V2S | sec_cm_timeout_clk_bkgn_chk | clkmgr_frequency_timeout | 0 | 50 | 0.00 | ||
| V2S | sec_cm_meas_config_shadow | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | sec_cm_idle_intersig_mubi | clkmgr_idle_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | clkmgr_lc_ctrl_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_clk_handshake_intersig_mubi | clkmgr_lc_clk_byp_req_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_clk_handshake_intersig_mubi | clkmgr_clk_handshake_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_div_intersig_mubi | clkmgr_div_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_jitter_config_mubi | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_idle_ctr_redun | clkmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_meas_config_regwen | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_clk_ctrl_config_regwen | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | prim_count_check | clkmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 0 | 315 | 0.00 | |||
| V3 | regwen | clkmgr_regwen | 0 | 50 | 0.00 | ||
| V3 | stress_all_with_rand_reset | clkmgr_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| TOTAL | 0 | 1010 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 11 | 11 | 0 | 0.00 |
| V2S | 9 | 9 | 0 | 0.00 |
| V3 | 2 | 2 | 0 | 0.00 |
User terminated with CTRL-C has 1010 failures:
0.clkmgr_smoke.102786154237185792667426583895905381245713388724746010482771943892080399856062
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_smoke/latest/run.log
1.clkmgr_smoke.32638880742597103085452691563039671193515496579697830076874176001374076650358
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_smoke/latest/run.log
... and 48 more failures.
0.clkmgr_extclk.60650924027801039099286893212726215968865527634891849065778079422026320617958
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_extclk/latest/run.log
1.clkmgr_extclk.30275428343637870544619559557253927970462168645371704092917311600280584767211
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_extclk/latest/run.log
... and 48 more failures.
0.clkmgr_frequency.42958765396675799259320245789058038465588094777696943626026439177994751072422
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_frequency/latest/run.log
1.clkmgr_frequency.25486168417122120547340394805059521263615841595759632571249284137106796631320
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_frequency/latest/run.log
... and 48 more failures.
0.clkmgr_frequency_timeout.113619275106223744058226771455459268894594529515946607223841184645439838355634
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log
1.clkmgr_frequency_timeout.81431214009673187545317485111622944898167347489329366876155210272247183456089
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest/run.log
... and 48 more failures.
0.clkmgr_peri.110818612749499608638057586233406919451512678347325913598132669947406386052299
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_peri/latest/run.log
1.clkmgr_peri.110164171902662087566658631363756347282435721215655459382649282108247184079935
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_peri/latest/run.log
... and 48 more failures.
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/cov_report/cov_report.log