CLKMGR Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.150s 132.459us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.130s 148.963us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 0.990s 119.509us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 7.560s 469.570us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.310s 278.288us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.200s 179.836us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 0.990s 119.509us 20 20 100.00
clkmgr_csr_aliasing 2.310s 278.288us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.950s 112.305us 50 50 100.00
V2 trans_enables clkmgr_trans 2.010s 435.008us 50 50 100.00
V2 extclk clkmgr_extclk 1.600s 268.765us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.050s 169.320us 50 50 100.00
V2 jitter clkmgr_smoke 1.150s 132.459us 50 50 100.00
V2 frequency clkmgr_frequency 17.880s 2.360ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.050s 2.421ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.880s 2.360ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.324m 11.589ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.770s 50.821us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.310s 233.971us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 3.730s 840.359us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 3.730s 840.359us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.130s 148.963us 5 5 100.00
clkmgr_csr_rw 0.990s 119.509us 20 20 100.00
clkmgr_csr_aliasing 2.310s 278.288us 5 5 100.00
clkmgr_same_csr_outstanding 1.570s 111.310us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.130s 148.963us 5 5 100.00
clkmgr_csr_rw 0.990s 119.509us 20 20 100.00
clkmgr_csr_aliasing 2.310s 278.288us 5 5 100.00
clkmgr_same_csr_outstanding 1.570s 111.310us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 4.340s 645.715us 5 5 100.00
clkmgr_tl_intg_err 4.410s 1.053ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.170s 575.863us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.170s 575.863us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.170s 575.863us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.170s 575.863us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 5.540s 1.004ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.410s 1.053ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.880s 2.360ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.050s 2.421ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.170s 575.863us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.440s 236.339us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.500s 260.932us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.220s 162.653us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.400s 247.566us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.380s 210.771us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 0.990s 119.509us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 4.340s 645.715us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 0.990s 119.509us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 0.990s 119.509us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 4.340s 645.715us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 23.207m 196.861ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 959 960 99.90

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.63 99.12 95.44 100.00 100.00 98.71 96.97 93.18

Failure Buckets

Past Results