CLKMGR Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 0.930s 32.797us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.890s 26.476us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 0.890s 27.744us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 8.270s 667.703us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.800s 93.350us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.210s 39.190us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 0.890s 27.744us 20 20 100.00
clkmgr_csr_aliasing 1.800s 93.350us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.850s 21.940us 50 50 100.00
V2 trans_enables clkmgr_trans 1.130s 52.118us 50 50 100.00
V2 extclk clkmgr_extclk 0.970s 39.279us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.840s 26.315us 50 50 100.00
V2 jitter clkmgr_smoke 0.930s 32.797us 50 50 100.00
V2 frequency clkmgr_frequency 13.870s 2.247ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 12.700s 2.187ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 13.870s 2.247ms 50 50 100.00
V2 stress_all clkmgr_stress_all 52.560s 9.642ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.730s 19.262us 50 50 100.00
V2 alert_test clkmgr_alert_test 0.880s 21.547us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 3.720s 200.117us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 3.720s 200.117us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.890s 26.476us 5 5 100.00
clkmgr_csr_rw 0.890s 27.744us 20 20 100.00
clkmgr_csr_aliasing 1.800s 93.350us 5 5 100.00
clkmgr_same_csr_outstanding 1.510s 74.654us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.890s 26.476us 5 5 100.00
clkmgr_csr_rw 0.890s 27.744us 20 20 100.00
clkmgr_csr_aliasing 1.800s 93.350us 5 5 100.00
clkmgr_same_csr_outstanding 1.510s 74.654us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.200s 376.652us 5 5 100.00
clkmgr_tl_intg_err 2.830s 175.885us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 1.930s 131.734us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 1.930s 131.734us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 1.930s 131.734us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 1.930s 131.734us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.000s 194.392us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 2.830s 175.885us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 13.870s 2.247ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 12.700s 2.187ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 1.930s 131.734us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.120s 54.815us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.010s 39.279us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 0.960s 36.529us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 0.990s 39.493us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 0.960s 39.279us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 0.890s 27.744us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.200s 376.652us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 0.890s 27.744us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 0.890s 27.744us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.200s 376.652us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 6.010s 1.250ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 15.229m 87.793ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.62 99.01 93.37 100.00 100.00 98.65 95.01 97.26

Past Results