---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_io_div2_meas.u_meas.MaxWidth_A	0	0	179703727	0	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	12023668	0	0	0
tb.dut.u_io_div4_meas.u_meas.MaxWidth_A	0	0	89851296	0	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	12023668	0	0	0
tb.dut.u_io_meas.u_meas.MaxWidth_A	0	0	358025355	0	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	12023668	0	0	0
tb.dut.u_main_meas.u_meas.MaxWidth_A	0	0	383006672	0	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	12023668	0	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	181036966	0	0	957
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	90517911	0	0	957
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	360784671	0	0	957
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	385881061	0	0	957
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	185157694	0	0	957
tb.dut.u_usb_meas.u_meas.MaxWidth_A	0	0	183778005	0	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	12023668	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnownO_A	0	0	139860077	138907117	0	0
tb.dut.AllClkBypReqKnownO_A	0	0	139860077	138907117	0	0
tb.dut.CgEnKnownO_A	0	0	139860077	138907117	0	0
tb.dut.ClocksKownO_A	0	0	139860077	138907117	0	0
tb.dut.FpvSecCmClkMainAesCountCheck_A	0	0	139860077	69	0	0
tb.dut.FpvSecCmClkMainHmacCountCheck_A	0	0	139860077	71	0	0
tb.dut.FpvSecCmClkMainKmacCountCheck_A	0	0	139860077	68	0	0
tb.dut.FpvSecCmClkMainOtbnCountCheck_A	0	0	139860077	72	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	139860077	100	0	0
tb.dut.IoClkBypReqKnownO_A	0	0	139860077	138907117	0	0
tb.dut.JitterEnableKnownO_A	0	0	139860077	138907117	0	0
tb.dut.LcCtrlClkBypAckKnownO_A	0	0	139860077	138907117	0	0
tb.dut.PwrMgrKnownO_A	0	0	139860077	138907117	0	0
tb.dut.TlAReadyKnownO_A	0	0	139860077	138907117	0	0
tb.dut.TlDValidKnownO_A	0	0	139860077	138907117	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStart_A	0	0	383007068	3667	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStop_A	0	0	383007068	1931	0	0
tb.dut.clkmgr_aon_cg_aon_peri.CgEn_A	0	0	752	752	0	0
tb.dut.clkmgr_aon_cg_aon_powerup.CgEn_A	0	0	752	752	0	0
tb.dut.clkmgr_aon_cg_aon_secure.CgEn_A	0	0	752	752	0	0
tb.dut.clkmgr_aon_cg_aon_timers.CgEn_A	0	0	752	752	0	0
tb.dut.clkmgr_aon_cg_io_div2_powerup.CgEn_A	0	0	752	752	0	0
tb.dut.clkmgr_aon_cg_io_div4_powerup.CgEn_A	0	0	752	752	0	0
tb.dut.clkmgr_aon_cg_io_powerup.CgEn_A	0	0	752	752	0	0
tb.dut.clkmgr_aon_cg_main_powerup.CgEn_A	0	0	752	752	0	0
tb.dut.clkmgr_aon_cg_usb_powerup.CgEn_A	0	0	752	752	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOff_A	0	0	179703727	156	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOn_A	0	0	179703727	156	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOff_A	0	0	179703727	6602	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOn_A	0	0	179703727	4719	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOff_A	0	0	89851296	156	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOn_A	0	0	89851296	156	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOff_A	0	0	89851296	5999	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOn_A	0	0	89851296	4118	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOff_A	0	0	89851296	156	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOn_A	0	0	89851296	156	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOff_A	0	0	89851296	156	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOn_A	0	0	89851296	156	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOff_A	0	0	358025355	156	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOn_A	0	0	358025355	150	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOff_A	0	0	358025355	6878	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOn_A	0	0	358025355	4991	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOff_A	0	0	383006672	3828	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOn_A	0	0	383006672	3830	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOff_A	0	0	383006672	3818	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOn_A	0	0	383006672	3815	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOff_A	0	0	383006672	161	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOn_A	0	0	383006672	158	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOff_A	0	0	383006672	3815	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOn_A	0	0	383006672	3813	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOff_A	0	0	383006672	3843	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOn_A	0	0	383006672	3841	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOff_A	0	0	383006672	161	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOn_A	0	0	383006672	158	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOff_A	0	0	183778005	6617	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOn_A	0	0	183778005	4730	0	0
tb.dut.clkmgr_csr_assert.TlulOOBAddrErr_A	0	0	140809801	4759706	0	0
tb.dut.clkmgr_csr_assert.clk_enables_rd_A	0	0	140809801	24183	0	0
tb.dut.clkmgr_csr_assert.clk_hints_rd_A	0	0	140809801	21732	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_rd_A	0	0	140809801	27850	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_regwen_rd_A	0	0	140809801	19335	0	0
tb.dut.clkmgr_csr_assert.jitter_enable_rd_A	0	0	140809801	34188	0	0
tb.dut.clkmgr_csr_assert.jitter_regwen_rd_A	0	0	140809801	22901	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Stepped_A	0	0	358025763	3902	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Whole_A	0	0	358025763	4681	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Stepped_A	0	0	179704105	3812	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Whole_A	0	0	179704105	4395	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqFall_A	0	0	139860077	3722	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqRise_A	0	0	139860077	3724	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelFall_A	0	0	139860077	2190	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelRise_A	0	0	139860077	2191	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqFall_A	0	0	139860077	4616	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqRise_A	0	0	139860077	4617	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStart_A	0	0	383007068	3657	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStop_A	0	0	383007068	1900	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateClose_A	0	0	179704105	3180	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateOpen_A	0	0	179704105	3180	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateClose_A	0	0	89851695	2871	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateOpen_A	0	0	89851695	2871	0	0
tb.dut.clkmgr_io_peri_sva_if.GateClose_A	0	0	358025763	3346	0	0
tb.dut.clkmgr_io_peri_sva_if.GateOpen_A	0	0	358025763	3346	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStart_A	0	0	383007068	3654	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStop_A	0	0	383007068	1882	0	0
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if.CtrlEnOn_A	0	0	139860077	11239	0	0
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if.CtrlEnOn_A	0	0	139860077	15328	0	0
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if.CtrlEnOn_A	0	0	139860077	23428	0	0
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if.CtrlEnOn_A	0	0	139860077	11039	0	0
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	139860077	16878859	0	58
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if.CtrlEnOn_A	0	0	139860077	15419	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStart_A	0	0	383007068	3682	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStop_A	0	0	383007068	1882	0	0
tb.dut.clkmgr_pwrmgr_sva_if.IoStatusFall_A	0	0	139860077	149	0	0
tb.dut.clkmgr_pwrmgr_sva_if.IoStatusRise_A	0	0	139860077	149	0	0
tb.dut.clkmgr_pwrmgr_sva_if.MainStatusFall_A	0	0	139860077	158	0	0
tb.dut.clkmgr_pwrmgr_sva_if.MainStatusRise_A	0	0	139860077	158	0	0
tb.dut.clkmgr_pwrmgr_sva_if.UsbStatusFall_A	0	0	139860077	155	0	0
tb.dut.clkmgr_pwrmgr_sva_if.UsbStatusRise_A	0	0	139860077	155	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqFalse_A	0	0	139860077	138794845	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqTrue_A	0	0	139860077	110382	0	0
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	139860077	138721299	0	2256
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqTrue_A	0	0	139860077	180148	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckFalse_A	0	0	139860077	138799767	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckTrue_A	0	0	139860077	105460	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateClose_A	0	0	183778428	3217	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateOpen_A	0	0	183778428	3217	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	140809801	18797324	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	140809801	139754691	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	140809801	139754691	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	140809801	15266942	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	140809801	139754691	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	140809801	139754691	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
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tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	957	957	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	140810398	15513092	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	140809801	2567797	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	140810398	192982	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	140810398	110576	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	140809801	2836013	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	140810398	18797358	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	140810398	15266977	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	140810398	18797358	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	140810398	15266977	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	140810398	15266977	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	140810398	15266977	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	140809801	1538140	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	140809801	1179974	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	957	957	0	0
tb.dut.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_calib_rdy_sync.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_clk_io_div2_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	139860077	138907117	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	139860077	138907117	0	0
tb.dut.u_clk_io_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clk_io_peri_scanmode_sync.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_clk_io_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	139860077	138907117	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.OutputsKnown_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	383006672	381537473	0	2256
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	383006672	30348	0	0
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.OutputsKnown_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.OutputsKnown_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	383006672	381537473	0	2256
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	383006672	30434	0	0
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.OutputsKnown_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	383006672	381537473	0	2256
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	383006672	30153	0	0
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.OutputsKnown_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	383006672	381537473	0	2256
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	383006672	30067	0	0
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.OutputsKnown_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	383006672	381543143	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	139860077	138907117	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	139860077	17432	0	0
tb.dut.u_clkmgr_byp.u_all_byp_req.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_clkmgr_byp.u_en_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clkmgr_byp.u_en_sync.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_clkmgr_byp.u_hi_speed_sel.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	139860077	15225	0	0
tb.dut.u_clkmgr_byp.u_io_byp_req.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_io_div2_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_io_div2_div_scanmode_sync.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_io_div2_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	139860077	138907117	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	139860077	3023	0	0
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckHoldReq	0	0	179703727	3023	0	0
tb.dut.u_io_div2_meas.u_meas.RefCntVal_A	0	0	752	752	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	179703727	2661948	0	0
tb.dut.u_io_div2_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	752	752	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	179703727	88599	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	11962669	88195	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	179703727	179703727	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	179703727	179703727	0	0
tb.dut.u_io_div4_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_io_div4_div_scanmode_sync.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_io_div4_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	139860077	138907117	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	139860077	2770	0	0
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckHoldReq	0	0	89851296	2770	0	0
tb.dut.u_io_div4_meas.u_meas.RefCntVal_A	0	0	752	752	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	89851296	2541696	0	0
tb.dut.u_io_div4_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	752	752	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	89851296	87609	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	11962669	87204	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	89851296	89851296	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	89851296	89851296	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_io_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	139860077	2999	0	0
tb.dut.u_io_meas.u_err_sync.SyncReqAckHoldReq	0	0	358025355	2999	0	0
tb.dut.u_io_meas.u_meas.RefCntVal_A	0	0	752	752	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	358025355	2662037	0	0
tb.dut.u_io_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	752	752	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	358025355	89021	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	11962669	88619	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	358025355	357372117	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	358025355	357372117	0	0
tb.dut.u_io_step_down_req_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_io_step_down_req_sync.OutputsKnown_A	0	0	358025355	356684529	0	0
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	358025355	356678859	0	2256
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	358025355	24865	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_main_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	139860077	2899	0	0
tb.dut.u_main_meas.u_err_sync.SyncReqAckHoldReq	0	0	383006672	2899	0	0
tb.dut.u_main_meas.u_meas.RefCntVal_A	0	0	752	752	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	383006672	2665868	0	0
tb.dut.u_main_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	752	752	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	383006672	106648	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	11923992	106014	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	383006672	382288596	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	383006672	382288596	0	0
tb.dut.u_no_scan_io_div2_div.DivEven_A	0	0	752	752	0	0
tb.dut.u_no_scan_io_div2_div.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown0	0	0	178686526	178685774	0	0
tb.dut.u_no_scan_io_div2_div.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown1	0	0	358025355	358024603	0	0
tb.dut.u_no_scan_io_div2_div.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	179703727	179702975	0	0
tb.dut.u_no_scan_io_div2_div.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	358025355	358024603	0	0
tb.dut.u_no_scan_io_div4_div.DivEven_A	0	0	752	752	0	0
tb.dut.u_no_scan_io_div4_div.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	89851296	89850544	0	0
tb.dut.u_no_scan_io_div4_div.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	358025355	358024603	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra.OutputsKnown_A	0	0	179703727	179359454	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri.OutputsKnown_A	0	0	179703727	179359454	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra.OutputsKnown_A	0	0	89851296	89679232	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri.OutputsKnown_A	0	0	89851296	89679232	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure.OutputsKnown_A	0	0	89851296	89679232	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers.OutputsKnown_A	0	0	89851296	89679232	0	0
tb.dut.u_prim_mubi4_sender_clk_io_infra.OutputsKnown_A	0	0	358025355	356684529	0	0
tb.dut.u_prim_mubi4_sender_clk_io_peri.OutputsKnown_A	0	0	358025355	356684529	0	0
tb.dut.u_prim_mubi4_sender_clk_main_infra.OutputsKnown_A	0	0	383006672	381543143	0	0
tb.dut.u_prim_mubi4_sender_clk_main_secure.OutputsKnown_A	0	0	383006672	381543143	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_infra.OutputsKnown_A	0	0	183778005	183091893	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_peri.OutputsKnown_A	0	0	183778005	183091893	0	0
tb.dut.u_reg.en2addrHit	0	0	140809801	758335	0	0
tb.dut.u_reg.reAfterRv	0	0	140809801	758331	0	0
tb.dut.u_reg.rePulse	0	0	140809801	173273	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	957	957	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	140809801	121375	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.DstReqKnown_A	0	0	181036966	180644126	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	140809801	23227	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	140809801	139754691	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	181036966	1140	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	140809801	24367	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	181036966	23226	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	181036966	23227	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	140809801	23228	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	140809801	146958	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	181036966	180644126	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	140809801	27940	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	140809801	139754691	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	140809801	27933	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	181036966	27950	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	181036966	27948	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	140809801	27966	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	957	957	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	140809801	36	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	181036966	36	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	957	957	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	140809801	37	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	181036966	37	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	140809801	195953	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.DstReqKnown_A	0	0	90517911	90321603	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	140809801	23225	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	140809801	139754691	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	90517911	1139	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	140809801	24364	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	90517911	23225	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	90517911	23225	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	140809801	23227	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	140809801	238075	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	90517911	90321603	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	140809801	27974	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	140809801	139754691	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	140809801	27971	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	90517911	27981	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	90517911	27973	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	140809801	28011	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	957	957	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	140809801	32	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	90517911	32	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	957	957	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	140809801	29	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	90517911	29	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	140809801	85214	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.DstReqKnown_A	0	0	360784671	359253916	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	140809801	23230	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	140809801	139754691	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	360784671	1140	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	140809801	24370	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	360784671	23230	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	360784671	23230	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	140809801	23230	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	140809801	102816	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	360784671	359253916	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	140809801	28003	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	140809801	139754691	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	140809801	28001	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	360784671	28016	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	360784671	28013	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	140809801	28032	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	957	957	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	140809801	35	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	360784671	35	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	957	957	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	140809801	34	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	360784671	34	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	140809801	83505	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.DstReqKnown_A	0	0	385881061	384219680	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	140809801	23225	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	140809801	139754691	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	385881061	1139	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	140809801	24364	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	385881061	23225	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	385881061	23225	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	140809801	23225	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	140809801	101378	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	385881061	384219680	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	140809801	28008	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	140809801	139754691	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	140809801	28007	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	385881061	28019	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	385881061	28015	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	140809801	28028	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	957	957	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	140809801	50	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	385881061	50	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	957	957	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	140809801	46	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	385881061	46	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	957	957	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	957	957	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	957	957	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	957	957	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	957	957	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	957	957	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	957	957	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	140809801	122358	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.DstReqKnown_A	0	0	185157694	184376651	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	140809801	23223	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	140809801	139754691	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	185157694	1139	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	140809801	24362	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	185157694	23222	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	185157694	23223	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	140809801	23223	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	140809801	148122	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	185157694	184376651	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	140809801	27989	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	140809801	139754691	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	140809801	27988	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	185157694	27997	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	185157694	27996	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	140809801	28026	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	957	957	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	140809801	36	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	185157694	36	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	957	957	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	140809801	46	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	185157694	46	0	0
tb.dut.u_reg.wePulse	0	0	140809801	585058	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	139860077	138907117	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_usb_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	139860077	2884	0	0
tb.dut.u_usb_meas.u_err_sync.SyncReqAckHoldReq	0	0	183778005	2884	0	0
tb.dut.u_usb_meas.u_meas.RefCntVal_A	0	0	752	752	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	183778005	2665818	0	0
tb.dut.u_usb_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	752	752	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	183778005	105260	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	11944706	103302	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	752	752	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	183778005	183439621	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	183778005	183439621	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	139860077	16878859	0	58
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	139860077	138721299	0	2256
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	383006672	381537473	0	2256
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	383006672	381537473	0	2256
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	383006672	381537473	0	2256
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	383006672	381537473	0	2256
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	358025355	356678859	0	2256
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	181036966	0	0	957
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	90517911	0	0	957
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	360784671	0	0	957
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	385881061	0	0	957
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	185157694	0	0	957
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	139860077	138901424	0	2256

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	140810398	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	140810398	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	140810398	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	140810398	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	140810398	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	140810398	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	140810398	6672	6672	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	140810398	3697	3697	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	140810398	14888	14888	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	140810398	81338	81338	705

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	140810398	6672	6672	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	140810398	3697	3697	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	140810398	14888	14888	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	140810398	81338	81338	705