---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_io_div2_meas.u_meas.MaxWidth_A	0	0	267369475	0	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	24453666	0	0	0
tb.dut.u_io_div4_meas.u_meas.MaxWidth_A	0	0	133684117	0	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	24453666	0	0	0
tb.dut.u_io_meas.u_meas.MaxWidth_A	0	0	533392165	0	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	24453666	0	0	0
tb.dut.u_main_meas.u_meas.MaxWidth_A	0	0	566749171	0	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	24453666	0	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	268669930	0	0	960
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	134334333	0	0	960
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	536095407	0	0	960
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	569565164	0	0	960
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	273412087	0	0	960
tb.dut.u_usb_meas.u_meas.MaxWidth_A	0	0	272060459	0	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	24453666	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnownO_A	0	0	180909152	180169556	0	0
tb.dut.AllClkBypReqKnownO_A	0	0	180909152	180169556	0	0
tb.dut.CgEnKnownO_A	0	0	180909152	180169556	0	0
tb.dut.ClocksKownO_A	0	0	180909152	180169556	0	0
tb.dut.FpvSecCmClkMainAesCountCheck_A	0	0	180909152	29	0	0
tb.dut.FpvSecCmClkMainHmacCountCheck_A	0	0	180909152	28	0	0
tb.dut.FpvSecCmClkMainKmacCountCheck_A	0	0	180909152	27	0	0
tb.dut.FpvSecCmClkMainOtbnCountCheck_A	0	0	180909152	29	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	180909152	80	0	0
tb.dut.IoClkBypReqKnownO_A	0	0	180909152	180169556	0	0
tb.dut.JitterEnableKnownO_A	0	0	180909152	180169556	0	0
tb.dut.LcCtrlClkBypAckKnownO_A	0	0	180909152	180169556	0	0
tb.dut.PwrMgrKnownO_A	0	0	180909152	180169556	0	0
tb.dut.TlAReadyKnownO_A	0	0	180909152	180169556	0	0
tb.dut.TlDValidKnownO_A	0	0	180909152	180169556	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStart_A	0	0	566749567	4042	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStop_A	0	0	566749567	2066	0	0
tb.dut.clkmgr_aon_cg_aon_peri.CgEn_A	0	0	755	755	0	0
tb.dut.clkmgr_aon_cg_aon_powerup.CgEn_A	0	0	755	755	0	0
tb.dut.clkmgr_aon_cg_aon_secure.CgEn_A	0	0	755	755	0	0
tb.dut.clkmgr_aon_cg_aon_timers.CgEn_A	0	0	755	755	0	0
tb.dut.clkmgr_aon_cg_io_div2_powerup.CgEn_A	0	0	755	755	0	0
tb.dut.clkmgr_aon_cg_io_div4_powerup.CgEn_A	0	0	755	755	0	0
tb.dut.clkmgr_aon_cg_io_powerup.CgEn_A	0	0	755	755	0	0
tb.dut.clkmgr_aon_cg_main_powerup.CgEn_A	0	0	755	755	0	0
tb.dut.clkmgr_aon_cg_usb_powerup.CgEn_A	0	0	755	755	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOff_A	0	0	267369475	141	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOn_A	0	0	267369475	141	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOff_A	0	0	267369475	7618	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOn_A	0	0	267369475	5796	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOff_A	0	0	133684117	141	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOn_A	0	0	133684117	141	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOff_A	0	0	133684117	7079	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOn_A	0	0	133684117	5260	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOff_A	0	0	133684117	141	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOn_A	0	0	133684117	141	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOff_A	0	0	133684117	141	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOn_A	0	0	133684117	141	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOff_A	0	0	533392165	141	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOn_A	0	0	533392165	135	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOff_A	0	0	533392165	7812	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOn_A	0	0	533392165	5987	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOff_A	0	0	566749171	4170	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOn_A	0	0	566749171	4172	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOff_A	0	0	566749171	4200	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOn_A	0	0	566749171	4203	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOff_A	0	0	566749171	128	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOn_A	0	0	566749171	128	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOff_A	0	0	566749171	4125	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOn_A	0	0	566749171	4129	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOff_A	0	0	566749171	4164	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOn_A	0	0	566749171	4167	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOff_A	0	0	566749171	128	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOn_A	0	0	566749171	128	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOff_A	0	0	272060459	7510	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOn_A	0	0	272060459	5683	0	0
tb.dut.clkmgr_csr_assert.TlulOOBAddrErr_A	0	0	181905536	6186987	0	0
tb.dut.clkmgr_csr_assert.clk_enables_rd_A	0	0	181905536	34872	0	0
tb.dut.clkmgr_csr_assert.clk_hints_rd_A	0	0	181905536	31128	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_rd_A	0	0	181905536	39101	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_regwen_rd_A	0	0	181905536	30078	0	0
tb.dut.clkmgr_csr_assert.jitter_enable_rd_A	0	0	181905536	45000	0	0
tb.dut.clkmgr_csr_assert.jitter_regwen_rd_A	0	0	181905536	33155	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Stepped_A	0	0	533392590	4578	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Whole_A	0	0	533392590	5464	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Stepped_A	0	0	267369867	4469	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Whole_A	0	0	267369867	5150	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqFall_A	0	0	180909152	4306	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqRise_A	0	0	180909152	4307	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelFall_A	0	0	180909152	2623	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelRise_A	0	0	180909152	2623	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqFall_A	0	0	180909152	5349	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqRise_A	0	0	180909152	5350	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStart_A	0	0	566749567	4072	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStop_A	0	0	566749567	2078	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateClose_A	0	0	267369867	3720	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateOpen_A	0	0	267369867	3720	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateClose_A	0	0	133684495	3439	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateOpen_A	0	0	133684495	3438	0	0
tb.dut.clkmgr_io_peri_sva_if.GateClose_A	0	0	533392590	3843	0	0
tb.dut.clkmgr_io_peri_sva_if.GateOpen_A	0	0	533392590	3841	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStart_A	0	0	566749567	3997	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStop_A	0	0	566749567	2042	0	0
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if.CtrlEnOn_A	0	0	180909152	12311	0	0
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if.CtrlEnOn_A	0	0	180909152	17054	0	0
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if.CtrlEnOn_A	0	0	180909152	26128	0	0
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if.CtrlEnOn_A	0	0	180909152	12271	0	0
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	180909152	19120677	0	58
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if.CtrlEnOn_A	0	0	180909152	17129	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStart_A	0	0	566749567	4036	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStop_A	0	0	566749567	2047	0	0
tb.dut.clkmgr_pwrmgr_sva_if.IoStatusFall_A	0	0	180909152	134	0	0
tb.dut.clkmgr_pwrmgr_sva_if.IoStatusRise_A	0	0	180909152	134	0	0
tb.dut.clkmgr_pwrmgr_sva_if.MainStatusFall_A	0	0	180909152	127	0	0
tb.dut.clkmgr_pwrmgr_sva_if.MainStatusRise_A	0	0	180909152	127	0	0
tb.dut.clkmgr_pwrmgr_sva_if.UsbStatusFall_A	0	0	180909152	133	0	0
tb.dut.clkmgr_pwrmgr_sva_if.UsbStatusRise_A	0	0	180909152	133	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqFalse_A	0	0	180909152	180037299	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqTrue_A	0	0	180909152	130428	0	0
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	180909152	179957207	0	2265
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqTrue_A	0	0	180909152	206862	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckFalse_A	0	0	180909152	180048480	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckTrue_A	0	0	180909152	119247	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateClose_A	0	0	272060857	3757	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateOpen_A	0	0	272060857	3757	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	181905536	23393325	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	181905536	181051610	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	181905536	181051610	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	181905536	20674290	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	181905536	181051610	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	181905536	181051610	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
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tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	960	960	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	181906151	19308212	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	181905536	3342316	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	181906151	189315	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	181906151	121650	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	181905536	3694765	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	181906151	23393366	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	181906151	20674317	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	181906151	23393366	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	181906151	20674317	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	181906151	20674317	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	181906151	20674317	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	181905536	1998665	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	181905536	1519409	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	960	960	0	0
tb.dut.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_calib_rdy_sync.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_clk_io_div2_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	180909152	180169556	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	180909152	180169556	0	0
tb.dut.u_clk_io_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clk_io_peri_scanmode_sync.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_clk_io_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	180909152	180169556	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.OutputsKnown_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	566749171	565414288	0	2265
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	566749171	33765	0	0
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.OutputsKnown_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.OutputsKnown_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	566749171	565414288	0	2265
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	566749171	34078	0	0
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.OutputsKnown_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	566749171	565414288	0	2265
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	566749171	33903	0	0
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.OutputsKnown_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	566749171	565414288	0	2265
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	566749171	33620	0	0
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.OutputsKnown_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	566749171	565419775	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	180909152	180169556	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	180909152	20233	0	0
tb.dut.u_clkmgr_byp.u_all_byp_req.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_clkmgr_byp.u_en_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clkmgr_byp.u_en_sync.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_clkmgr_byp.u_hi_speed_sel.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	180909152	17810	0	0
tb.dut.u_clkmgr_byp.u_io_byp_req.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_io_div2_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_io_div2_div_scanmode_sync.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_io_div2_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	180909152	180169556	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	180909152	3070	0	0
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckHoldReq	0	0	267369475	3070	0	0
tb.dut.u_io_div2_meas.u_meas.RefCntVal_A	0	0	755	755	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	267369475	5423176	0	0
tb.dut.u_io_div2_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	755	755	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	267369475	97827	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	24262861	97160	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	267369475	267369475	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	267369475	267369475	0	0
tb.dut.u_io_div4_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_io_div4_div_scanmode_sync.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_io_div4_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	180909152	180169556	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	180909152	2951	0	0
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckHoldReq	0	0	133684117	2951	0	0
tb.dut.u_io_div4_meas.u_meas.RefCntVal_A	0	0	755	755	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	133684117	5166917	0	0
tb.dut.u_io_div4_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	755	755	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	133684117	97005	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	24262861	96339	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	133684117	133684117	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	133684117	133684117	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_io_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	180909152	3301	0	0
tb.dut.u_io_meas.u_err_sync.SyncReqAckHoldReq	0	0	533392165	3301	0	0
tb.dut.u_io_meas.u_meas.RefCntVal_A	0	0	755	755	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	533392165	5423294	0	0
tb.dut.u_io_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	755	755	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	533392165	98195	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	24262861	97528	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	533392165	532826203	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	533392165	532826203	0	0
tb.dut.u_io_step_down_req_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_io_step_down_req_sync.OutputsKnown_A	0	0	533392165	532194822	0	0
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	533392165	532189335	0	2265
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	533392165	28586	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_main_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	180909152	2852	0	0
tb.dut.u_main_meas.u_err_sync.SyncReqAckHoldReq	0	0	566749171	2852	0	0
tb.dut.u_main_meas.u_meas.RefCntVal_A	0	0	755	755	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	566749171	5427582	0	0
tb.dut.u_main_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	755	755	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	566749171	118081	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	24375328	117770	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	566749171	566118666	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	566749171	566118666	0	0
tb.dut.u_no_scan_io_div2_div.DivEven_A	0	0	755	755	0	0
tb.dut.u_no_scan_io_div2_div.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown0	0	0	266413558	266412803	0	0
tb.dut.u_no_scan_io_div2_div.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown1	0	0	533392165	533391410	0	0
tb.dut.u_no_scan_io_div2_div.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	267369475	267368720	0	0
tb.dut.u_no_scan_io_div2_div.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	533392165	533391410	0	0
tb.dut.u_no_scan_io_div4_div.DivEven_A	0	0	755	755	0	0
tb.dut.u_no_scan_io_div4_div.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	133684117	133683362	0	0
tb.dut.u_no_scan_io_div4_div.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	533392165	533391410	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra.OutputsKnown_A	0	0	267369475	267053330	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri.OutputsKnown_A	0	0	267369475	267053330	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra.OutputsKnown_A	0	0	133684117	133526095	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri.OutputsKnown_A	0	0	133684117	133526095	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure.OutputsKnown_A	0	0	133684117	133526095	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers.OutputsKnown_A	0	0	133684117	133526095	0	0
tb.dut.u_prim_mubi4_sender_clk_io_infra.OutputsKnown_A	0	0	533392165	532194822	0	0
tb.dut.u_prim_mubi4_sender_clk_io_peri.OutputsKnown_A	0	0	533392165	532194822	0	0
tb.dut.u_prim_mubi4_sender_clk_main_infra.OutputsKnown_A	0	0	566749171	565419775	0	0
tb.dut.u_prim_mubi4_sender_clk_main_secure.OutputsKnown_A	0	0	566749171	565419775	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_infra.OutputsKnown_A	0	0	272060459	271418072	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_peri.OutputsKnown_A	0	0	272060459	271418072	0	0
tb.dut.u_reg.en2addrHit	0	0	181905536	892378	0	0
tb.dut.u_reg.reAfterRv	0	0	181905536	892374	0	0
tb.dut.u_reg.rePulse	0	0	181905536	200312	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	960	960	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	181905536	134278	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.DstReqKnown_A	0	0	268669930	268303210	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	181905536	25509	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	181905536	181051610	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	268669930	1259	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	181905536	26768	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	268669930	25508	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	268669930	25509	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	181905536	25509	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	181905536	162288	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	268669930	268303210	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	181905536	30637	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	181905536	181051610	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	181905536	30636	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	268669930	30650	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	268669930	30646	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	181905536	30675	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	960	960	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	181905536	48	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	268669930	48	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	960	960	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	181905536	43	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	268669930	43	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	181905536	216498	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.DstReqKnown_A	0	0	134334333	134151071	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	181905536	25506	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	181905536	181051610	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	134334333	1259	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	181905536	26765	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	134334333	25506	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	134334333	25506	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	181905536	25506	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	181905536	262740	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	134334333	134151071	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	181905536	30658	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	181905536	181051610	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	181905536	30654	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	134334333	30668	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	134334333	30661	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	181905536	30690	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	960	960	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	181905536	35	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	134334333	35	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	960	960	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	181905536	41	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	134334333	41	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	181905536	92247	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.DstReqKnown_A	0	0	536095407	534694618	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	181905536	25510	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	181905536	181051610	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	536095407	1259	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	181905536	26769	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	536095407	25510	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	536095407	25510	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	181905536	25510	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	181905536	111682	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	536095407	534694618	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	181905536	30722	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	181905536	181051610	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	181905536	30717	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	536095407	30742	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	536095407	30739	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	181905536	30752	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	960	960	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	181905536	42	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	536095407	42	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	960	960	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	181905536	37	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	536095407	37	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	181905536	92506	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.DstReqKnown_A	0	0	569565164	568023821	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	181905536	25505	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	181905536	181051610	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	569565164	1259	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	181905536	26764	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	569565164	25505	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	569565164	25505	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	181905536	25505	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	181905536	111835	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	569565164	568023821	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	181905536	30709	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	181905536	181051610	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	181905536	30709	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	569565164	30728	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	569565164	30723	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	181905536	30741	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	960	960	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	181905536	38	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	569565164	38	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	960	960	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	181905536	37	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	569565164	37	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	960	960	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	960	960	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	960	960	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	960	960	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	960	960	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	960	960	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	960	960	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	181905536	135190	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.DstReqKnown_A	0	0	273412087	272668007	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	181905536	25504	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	181905536	181051610	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	273412087	1259	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	181905536	26763	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	273412087	25504	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	273412087	25504	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	181905536	25504	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	181905536	163280	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	273412087	272668007	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	181905536	30672	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	181905536	181051610	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	181905536	30669	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	273412087	30686	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	273412087	30681	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	181905536	30717	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	960	960	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	181905536	42	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	273412087	42	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	960	960	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	181905536	35	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	273412087	35	0	0
tb.dut.u_reg.wePulse	0	0	181905536	692062	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	180909152	180169556	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_usb_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	180909152	3008	0	0
tb.dut.u_usb_meas.u_err_sync.SyncReqAckHoldReq	0	0	272060459	3008	0	0
tb.dut.u_usb_meas.u_meas.RefCntVal_A	0	0	755	755	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	272060459	5427533	0	0
tb.dut.u_usb_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	755	755	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	272060459	117175	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	24438805	116975	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	755	755	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	272060459	271754992	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	272060459	271754992	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	180909152	19120677	0	58
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	180909152	179957207	0	2265
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	566749171	565414288	0	2265
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	566749171	565414288	0	2265
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	566749171	565414288	0	2265
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	566749171	565414288	0	2265
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	533392165	532189335	0	2265
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	268669930	0	0	960
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	134334333	0	0	960
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	536095407	0	0	960
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	569565164	0	0	960
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	273412087	0	0	960
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	180909152	180164063	0	2265

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	181906151	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	181906151	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	181906151	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	181906151	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	181906151	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	181906151	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	181906151	7281	7281	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	181906151	3341	3341	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	181906151	13525	13525	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	181906151	84029	84029	705

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	181906151	7281	7281	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	181906151	3341	3341	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	181906151	13525	13525	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	181906151	84029	84029	705