---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_io_div2_meas.u_meas.MaxWidth_A	0	0	212124502	0	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	16905009	0	0	0
tb.dut.u_io_div4_meas.u_meas.MaxWidth_A	0	0	106061712	0	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	16905009	0	0	0
tb.dut.u_io_meas.u_meas.MaxWidth_A	0	0	424349292	0	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	16905009	0	0	0
tb.dut.u_main_meas.u_meas.MaxWidth_A	0	0	452153794	0	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	16905009	0	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	213271358	0	0	959
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	106635145	0	0	959
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	426753211	0	0	959
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	454657984	0	0	959
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	218280931	0	0	959
tb.dut.u_usb_meas.u_meas.MaxWidth_A	0	0	217078936	0	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	16905009	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnownO_A	0	0	147211230	146358409	0	0
tb.dut.AllClkBypReqKnownO_A	0	0	147211230	146358409	0	0
tb.dut.CgEnKnownO_A	0	0	147211230	146358409	0	0
tb.dut.ClocksKownO_A	0	0	147211230	146358409	0	0
tb.dut.FpvSecCmClkMainAesCountCheck_A	0	0	147211230	39	0	0
tb.dut.FpvSecCmClkMainHmacCountCheck_A	0	0	147211230	39	0	0
tb.dut.FpvSecCmClkMainKmacCountCheck_A	0	0	147211230	40	0	0
tb.dut.FpvSecCmClkMainOtbnCountCheck_A	0	0	147211230	40	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	147211230	90	0	0
tb.dut.IoClkBypReqKnownO_A	0	0	147211230	146358409	0	0
tb.dut.JitterEnableKnownO_A	0	0	147211230	146358409	0	0
tb.dut.LcCtrlClkBypAckKnownO_A	0	0	147211230	146358409	0	0
tb.dut.PwrMgrKnownO_A	0	0	147211230	146358409	0	0
tb.dut.TlAReadyKnownO_A	0	0	147211230	146358409	0	0
tb.dut.TlDValidKnownO_A	0	0	147211230	146358409	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStart_A	0	0	452154199	3735	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStop_A	0	0	452154199	1885	0	0
tb.dut.clkmgr_aon_cg_aon_peri.CgEn_A	0	0	754	754	0	0
tb.dut.clkmgr_aon_cg_aon_powerup.CgEn_A	0	0	754	754	0	0
tb.dut.clkmgr_aon_cg_aon_secure.CgEn_A	0	0	754	754	0	0
tb.dut.clkmgr_aon_cg_aon_timers.CgEn_A	0	0	754	754	0	0
tb.dut.clkmgr_aon_cg_io_div2_powerup.CgEn_A	0	0	754	754	0	0
tb.dut.clkmgr_aon_cg_io_div4_powerup.CgEn_A	0	0	754	754	0	0
tb.dut.clkmgr_aon_cg_io_powerup.CgEn_A	0	0	754	754	0	0
tb.dut.clkmgr_aon_cg_main_powerup.CgEn_A	0	0	754	754	0	0
tb.dut.clkmgr_aon_cg_usb_powerup.CgEn_A	0	0	754	754	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOff_A	0	0	212124502	149	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOn_A	0	0	212124502	149	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOff_A	0	0	212124502	6319	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOn_A	0	0	212124502	4521	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOff_A	0	0	106061712	149	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOn_A	0	0	106061712	149	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOff_A	0	0	106061712	5957	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOn_A	0	0	106061712	4159	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOff_A	0	0	106061712	149	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOn_A	0	0	106061712	149	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOff_A	0	0	106061712	149	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOn_A	0	0	106061712	149	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOff_A	0	0	424349292	149	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOn_A	0	0	424349292	145	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOff_A	0	0	424349292	6486	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOn_A	0	0	424349292	4685	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOff_A	0	0	452153794	3887	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOn_A	0	0	452153794	3885	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOff_A	0	0	452153794	3900	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOn_A	0	0	452153794	3899	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOff_A	0	0	452153794	152	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOn_A	0	0	452153794	149	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOff_A	0	0	452153794	3892	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOn_A	0	0	452153794	3891	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOff_A	0	0	452153794	3847	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOn_A	0	0	452153794	3845	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOff_A	0	0	452153794	152	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOn_A	0	0	452153794	149	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOff_A	0	0	217078936	6312	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOn_A	0	0	217078936	4512	0	0
tb.dut.clkmgr_csr_assert.TlulOOBAddrErr_A	0	0	148209772	4544923	0	0
tb.dut.clkmgr_csr_assert.clk_enables_rd_A	0	0	148209772	60541	0	0
tb.dut.clkmgr_csr_assert.clk_hints_rd_A	0	0	148209772	54598	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_rd_A	0	0	148209772	63245	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_regwen_rd_A	0	0	148209772	51177	0	0
tb.dut.clkmgr_csr_assert.jitter_enable_rd_A	0	0	148209772	71606	0	0
tb.dut.clkmgr_csr_assert.jitter_regwen_rd_A	0	0	148209772	58319	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Stepped_A	0	0	424349679	3818	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Whole_A	0	0	424349679	4523	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Stepped_A	0	0	212124898	3745	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Whole_A	0	0	212124898	4273	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqFall_A	0	0	147211230	3550	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqRise_A	0	0	147211230	3551	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelFall_A	0	0	147211230	2083	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelRise_A	0	0	147211230	2084	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqFall_A	0	0	147211230	4523	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqRise_A	0	0	147211230	4522	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStart_A	0	0	452154199	3748	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStop_A	0	0	452154199	1906	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateClose_A	0	0	212124898	2946	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateOpen_A	0	0	212124898	2946	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateClose_A	0	0	106062092	2740	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateOpen_A	0	0	106062092	2739	0	0
tb.dut.clkmgr_io_peri_sva_if.GateClose_A	0	0	424349679	3023	0	0
tb.dut.clkmgr_io_peri_sva_if.GateOpen_A	0	0	424349679	3022	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStart_A	0	0	452154199	3740	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStop_A	0	0	452154199	1876	0	0
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if.CtrlEnOn_A	0	0	147211230	10655	0	0
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if.CtrlEnOn_A	0	0	147211230	14510	0	0
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if.CtrlEnOn_A	0	0	147211230	22086	0	0
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if.CtrlEnOn_A	0	0	147211230	10537	0	0
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	147211230	16297488	0	57
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if.CtrlEnOn_A	0	0	147211230	14577	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStart_A	0	0	452154199	3695	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStop_A	0	0	452154199	1861	0	0
tb.dut.clkmgr_pwrmgr_sva_if.IoStatusFall_A	0	0	147211230	145	0	0
tb.dut.clkmgr_pwrmgr_sva_if.IoStatusRise_A	0	0	147211230	145	0	0
tb.dut.clkmgr_pwrmgr_sva_if.MainStatusFall_A	0	0	147211230	148	0	0
tb.dut.clkmgr_pwrmgr_sva_if.MainStatusRise_A	0	0	147211230	148	0	0
tb.dut.clkmgr_pwrmgr_sva_if.UsbStatusFall_A	0	0	147211230	143	0	0
tb.dut.clkmgr_pwrmgr_sva_if.UsbStatusRise_A	0	0	147211230	143	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqFalse_A	0	0	147211230	146241035	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqTrue_A	0	0	147211230	115570	0	0
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	147211230	146167098	0	2262
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqTrue_A	0	0	147211230	185899	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckFalse_A	0	0	147211230	146248598	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckTrue_A	0	0	147211230	108007	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateClose_A	0	0	217079322	2966	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateOpen_A	0	0	217079322	2965	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	148209772	18234930	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	148209772	147225957	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	148209772	147225957	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	148209772	22550535	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	148209772	147225957	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	148209772	147225957	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
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tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	959	959	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	148210371	15021881	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	148209772	2442449	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	148210371	198685	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	148210371	126377	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	148209772	2706220	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	148210371	18234964	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	148210371	22550570	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	148210371	18234964	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	148210371	22550570	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	148210371	22550570	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	148210371	22550570	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	148209772	1460112	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	148209772	1108551	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	959	959	0	0
tb.dut.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_calib_rdy_sync.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_clk_io_div2_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	147211230	146358409	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	147211230	146358409	0	0
tb.dut.u_clk_io_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clk_io_peri_scanmode_sync.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_clk_io_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	147211230	146358409	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.OutputsKnown_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	452153794	450801137	0	2262
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	452153794	29821	0	0
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.OutputsKnown_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.OutputsKnown_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	452153794	450801137	0	2262
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	452153794	29671	0	0
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.OutputsKnown_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	452153794	450801137	0	2262
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	452153794	29597	0	0
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.OutputsKnown_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	452153794	450801137	0	2262
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	452153794	29894	0	0
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.OutputsKnown_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	452153794	450806549	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	147211230	146358409	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	147211230	16953	0	0
tb.dut.u_clkmgr_byp.u_all_byp_req.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_clkmgr_byp.u_en_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clkmgr_byp.u_en_sync.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_clkmgr_byp.u_hi_speed_sel.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	147211230	15156	0	0
tb.dut.u_clkmgr_byp.u_io_byp_req.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_io_div2_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_io_div2_div_scanmode_sync.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_io_div2_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	147211230	146358409	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	147211230	2962	0	0
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckHoldReq	0	0	212124502	2962	0	0
tb.dut.u_io_div2_meas.u_meas.RefCntVal_A	0	0	754	754	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	212124502	3746618	0	0
tb.dut.u_io_div2_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	754	754	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	212124502	89313	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	16780234	88427	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	212124502	212124502	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	212124502	212124502	0	0
tb.dut.u_io_div4_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_io_div4_div_scanmode_sync.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_io_div4_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	147211230	146358409	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	147211230	2790	0	0
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckHoldReq	0	0	106061712	2790	0	0
tb.dut.u_io_div4_meas.u_meas.RefCntVal_A	0	0	754	754	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	106061712	3575638	0	0
tb.dut.u_io_div4_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	754	754	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	106061712	88190	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	16780234	87317	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	106061712	106061712	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	106061712	106061712	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_io_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	147211230	2981	0	0
tb.dut.u_io_meas.u_err_sync.SyncReqAckHoldReq	0	0	424349292	2981	0	0
tb.dut.u_io_meas.u_meas.RefCntVal_A	0	0	754	754	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	424349292	3746737	0	0
tb.dut.u_io_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	754	754	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	424349292	89922	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	16780234	89029	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	424349292	423741777	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	424349292	423741777	0	0
tb.dut.u_io_step_down_req_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_io_step_down_req_sync.OutputsKnown_A	0	0	424349292	423111778	0	0
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	424349292	423106366	0	2262
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	424349292	24069	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_main_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	147211230	2844	0	0
tb.dut.u_main_meas.u_err_sync.SyncReqAckHoldReq	0	0	452153794	2844	0	0
tb.dut.u_main_meas.u_meas.RefCntVal_A	0	0	754	754	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	452153794	3750643	0	0
tb.dut.u_main_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	754	754	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	452153794	107149	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	16822144	105855	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	452153794	451478913	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	452153794	451478913	0	0
tb.dut.u_no_scan_io_div2_div.DivEven_A	0	0	754	754	0	0
tb.dut.u_no_scan_io_div2_div.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown0	0	0	211871322	211870568	0	0
tb.dut.u_no_scan_io_div2_div.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown1	0	0	424349292	424348538	0	0
tb.dut.u_no_scan_io_div2_div.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	212124502	212123748	0	0
tb.dut.u_no_scan_io_div2_div.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	424349292	424348538	0	0
tb.dut.u_no_scan_io_div4_div.DivEven_A	0	0	754	754	0	0
tb.dut.u_no_scan_io_div4_div.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	106061712	106060958	0	0
tb.dut.u_no_scan_io_div4_div.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	424349292	424348538	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra.OutputsKnown_A	0	0	212124502	211809069	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri.OutputsKnown_A	0	0	212124502	211809069	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra.OutputsKnown_A	0	0	106061712	105904046	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri.OutputsKnown_A	0	0	106061712	105904046	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure.OutputsKnown_A	0	0	106061712	105904046	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers.OutputsKnown_A	0	0	106061712	105904046	0	0
tb.dut.u_prim_mubi4_sender_clk_io_infra.OutputsKnown_A	0	0	424349292	423111778	0	0
tb.dut.u_prim_mubi4_sender_clk_io_peri.OutputsKnown_A	0	0	424349292	423111778	0	0
tb.dut.u_prim_mubi4_sender_clk_main_infra.OutputsKnown_A	0	0	452153794	450806549	0	0
tb.dut.u_prim_mubi4_sender_clk_main_secure.OutputsKnown_A	0	0	452153794	450806549	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_infra.OutputsKnown_A	0	0	217078936	216423508	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_peri.OutputsKnown_A	0	0	217078936	216423508	0	0
tb.dut.u_reg.en2addrHit	0	0	148209772	742412	0	0
tb.dut.u_reg.reAfterRv	0	0	148209772	742409	0	0
tb.dut.u_reg.rePulse	0	0	148209772	175756	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	959	959	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	148209772	118808	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.DstReqKnown_A	0	0	213271358	212900153	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	148209772	22656	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	148209772	147225957	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	213271358	1094	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	148209772	23750	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	213271358	22656	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	213271358	22656	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	148209772	22656	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	148209772	145127	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	213271358	212900153	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	148209772	27379	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	148209772	147225957	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	148209772	27374	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	213271358	27386	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	213271358	27384	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	148209772	27416	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	959	959	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	148209772	48	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	213271358	48	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	959	959	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	148209772	51	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	213271358	51	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	148209772	192107	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.DstReqKnown_A	0	0	106635145	106449677	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	148209772	22656	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	148209772	147225957	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	106635145	1094	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	148209772	23750	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	106635145	22655	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	106635145	22656	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	148209772	22656	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	148209772	237136	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	106635145	106449677	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	148209772	27478	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	148209772	147225957	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	148209772	27475	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	106635145	27480	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	106635145	27479	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	148209772	27529	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	959	959	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	148209772	57	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	106635145	57	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	959	959	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	148209772	52	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	106635145	52	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	148209772	82846	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.DstReqKnown_A	0	0	426753211	425294049	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	148209772	22660	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	148209772	147225957	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	426753211	1095	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	148209772	23755	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	426753211	22660	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	426753211	22660	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	148209772	22660	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	148209772	101659	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	426753211	425294049	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	148209772	27470	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	148209772	147225957	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	148209772	27462	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	426753211	27479	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	426753211	27478	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	148209772	27492	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	959	959	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	148209772	45	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	426753211	45	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	959	959	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	148209772	46	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	426753211	46	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	148209772	82096	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.DstReqKnown_A	0	0	454657984	453079834	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	148209772	22654	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	148209772	147225957	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	454657984	1094	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	148209772	23748	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	454657984	22654	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	454657984	22655	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	148209772	22655	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	148209772	100646	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	454657984	453079834	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	148209772	27468	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	148209772	147225957	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	148209772	27466	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	454657984	27478	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	454657984	27476	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	148209772	27495	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	959	959	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	148209772	43	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	454657984	43	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	959	959	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	148209772	49	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	454657984	49	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	959	959	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	959	959	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	959	959	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	959	959	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	959	959	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	959	959	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	959	959	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	148209772	119548	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.DstReqKnown_A	0	0	218280931	217514705	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	148209772	22654	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	148209772	147225957	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	218280931	1094	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	148209772	23748	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	218280931	22654	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	218280931	22654	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	148209772	22654	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	148209772	146004	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	218280931	217514705	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	148209772	27402	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	148209772	147225957	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	148209772	27398	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	218280931	27411	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	218280931	27409	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	148209772	27430	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	959	959	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	148209772	50	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	218280931	50	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	959	959	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	148209772	51	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	218280931	51	0	0
tb.dut.u_reg.wePulse	0	0	148209772	566653	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	147211230	146358409	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_usb_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	147211230	2570	0	0
tb.dut.u_usb_meas.u_err_sync.SyncReqAckHoldReq	0	0	217078936	2570	0	0
tb.dut.u_usb_meas.u_meas.RefCntVal_A	0	0	754	754	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	217078936	3750550	0	0
tb.dut.u_usb_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	754	754	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	217078936	105715	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	16838508	105114	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	754	754	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	217078936	216754359	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	217078936	216754359	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	147211230	16297488	0	57
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	147211230	146167098	0	2262
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	452153794	450801137	0	2262
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	452153794	450801137	0	2262
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	452153794	450801137	0	2262
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	452153794	450801137	0	2262
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	424349292	423106366	0	2262
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	213271358	0	0	959
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	106635145	0	0	959
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	426753211	0	0	959
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	454657984	0	0	959
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	218280931	0	0	959
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	147211230	146352997	0	2262

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	148210371	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	148210371	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	148210371	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	148210371	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	148210371	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	148210371	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	148210371	7349	7349	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	148210371	2637	2637	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	148210371	17966	17966	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	148210371	68581	68581	705

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	148210371	7349	7349	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	148210371	2637	2637	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	148210371	17966	17966	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	148210371	68581	68581	705