Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	609822	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3475023

1

T6

1

T4

53

T7

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1003636	1			T4	6		T28	45		T29	113
values[0x0]	1416322	1			T6	4		T4	50		T7	9
values[0x1]	1664887	1			T6	3		T4	77		T7	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	337996	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3746849

1

T6

2

T4

80

T7

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17154	1			T24	1		T29	1		T31	1
valid_sources[0x01]	16424	1			T64	1		T94	17		T69	1
valid_sources[0x02]	16253	1			T29	1		T64	3		T44	4
valid_sources[0x03]	16970	1			T6	4		T64	2		T65	1
valid_sources[0x04]	15382	1			T4	3		T29	1		T64	1
valid_sources[0x05]	14829	1			T29	1		T32	1		T64	1
valid_sources[0x06]	17583	1			T29	1		T64	4		T65	2
valid_sources[0x07]	14897	1			T29	3		T33	2		T64	2
valid_sources[0x08]	17541	1			T4	5		T29	1		T31	1
valid_sources[0x09]	18058	1			T29	1		T32	1		T43	1
valid_sources[0x0a]	15682	1			T32	1		T43	1		T64	5
valid_sources[0x0b]	15460	1			T4	9		T32	3		T43	2
valid_sources[0x0c]	16955	1			T28	5		T29	1		T32	2
valid_sources[0x0d]	16988	1			T29	1		T32	2		T64	1
valid_sources[0x0e]	16098	1			T29	2		T32	1		T44	6
valid_sources[0x0f]	16298	1			T4	3		T32	2		T43	3
valid_sources[0x10]	16278	1			T29	1		T33	1		T64	2
valid_sources[0x11]	15592	1			T28	7		T29	2		T32	1
valid_sources[0x12]	16057	1			T29	1		T43	1		T64	6
valid_sources[0x13]	16739	1			T65	2		T94	30		T45	9
valid_sources[0x14]	16578	1			T28	1		T43	2		T64	1
valid_sources[0x15]	15660	1			T29	2		T31	1		T64	5
valid_sources[0x16]	15691	1			T29	1		T43	3		T65	1
valid_sources[0x17]	15393	1			T43	2		T64	1		T65	2
valid_sources[0x18]	14981	1			T7	21		T29	1		T43	1
valid_sources[0x19]	15785	1			T94	13		T45	7		T68	2
valid_sources[0x1a]	15684	1			T29	1		T44	4		T94	7
valid_sources[0x1b]	17002	1			T64	1		T94	8		T45	23
valid_sources[0x1c]	16178	1			T31	3		T32	1		T42	3
valid_sources[0x1d]	15437	1			T33	1		T42	2		T43	1
valid_sources[0x1e]	16961	1			T4	2		T32	2		T43	1
valid_sources[0x1f]	15412	1			T65	3		T67	27		T94	15
valid_sources[0x20]	15959	1			T29	1		T31	2		T33	2
valid_sources[0x21]	15627	1			T4	4		T29	1		T32	2
valid_sources[0x22]	16052	1			T32	1		T42	6		T43	1
valid_sources[0x23]	15096	1			T64	3		T65	1		T94	21
valid_sources[0x24]	16218	1			T31	2		T43	1		T64	2
valid_sources[0x25]	14968	1			T4	9		T31	2		T43	1
valid_sources[0x26]	15575	1			T24	1		T43	1		T44	1
valid_sources[0x27]	16063	1			T28	5		T29	1		T32	1
valid_sources[0x28]	14797	1			T29	1		T32	1		T65	1
valid_sources[0x29]	17321	1			T31	1		T33	1		T43	1
valid_sources[0x2a]	14787	1			T29	3		T32	1		T43	1
valid_sources[0x2b]	16175	1			T29	1		T32	1		T43	1
valid_sources[0x2c]	16182	1			T4	1		T29	1		T43	3
valid_sources[0x2d]	15177	1			T29	1		T43	1		T64	5
valid_sources[0x2e]	16350	1			T32	2		T43	2		T64	3
valid_sources[0x2f]	15278	1			T29	2		T31	1		T32	2
valid_sources[0x30]	16615	1			T24	1		T29	1		T32	2
valid_sources[0x31]	14989	1			T29	2		T32	4		T43	2
valid_sources[0x32]	16255	1			T4	1		T32	1		T33	1
valid_sources[0x33]	15355	1			T29	3		T32	1		T43	3
valid_sources[0x34]	17942	1			T32	1		T43	1		T64	2
valid_sources[0x35]	15909	1			T29	1		T32	1		T64	1
valid_sources[0x36]	16138	1			T43	1		T64	4		T44	9
valid_sources[0x37]	15571	1			T43	1		T64	1		T44	3
valid_sources[0x38]	15404	1			T29	2		T32	1		T43	1
valid_sources[0x39]	15014	1			T29	1		T65	1		T81	1
valid_sources[0x3a]	14923	1			T29	2		T31	2		T44	1
valid_sources[0x3b]	15415	1			T31	1		T32	1		T43	1
valid_sources[0x3c]	16684	1			T33	3		T64	6		T44	4
valid_sources[0x3d]	15749	1			T28	6		T29	2		T32	2
valid_sources[0x3e]	15748	1			T4	3		T29	2		T32	1
valid_sources[0x3f]	16204	1			T32	1		T64	2		T44	5
valid_sources[0x40]	16414	1			T29	2		T43	1		T64	3
valid_sources[0x41]	16176	1			T28	3		T43	1		T64	1
valid_sources[0x42]	16180	1			T28	4		T29	2		T32	2
valid_sources[0x43]	14986	1			T4	13		T29	1		T32	1
valid_sources[0x44]	16658	1			T29	1		T31	2		T32	1
valid_sources[0x45]	17158	1			T29	1		T31	1		T32	2
valid_sources[0x46]	15548	1			T32	2		T43	1		T64	2
valid_sources[0x47]	16130	1			T32	1		T42	6		T43	2
valid_sources[0x48]	16575	1			T28	39		T32	1		T43	1
valid_sources[0x49]	17025	1			T29	1		T33	1		T64	4
valid_sources[0x4a]	16416	1			T32	1		T42	3		T43	1
valid_sources[0x4b]	15833	1			T32	1		T43	3		T64	3
valid_sources[0x4c]	16754	1			T29	2		T33	1		T43	1
valid_sources[0x4d]	15818	1			T31	1		T32	1		T44	4
valid_sources[0x4e]	15146	1			T29	2		T43	1		T64	3
valid_sources[0x4f]	16908	1			T31	6		T65	1		T94	8
valid_sources[0x50]	14911	1			T29	1		T32	1		T64	7
valid_sources[0x51]	15340	1			T29	2		T43	1		T64	6
valid_sources[0x52]	14755	1			T29	1		T32	2		T64	1
valid_sources[0x53]	17551	1			T29	1		T31	5		T64	1
valid_sources[0x54]	15026	1			T28	1		T32	1		T33	1
valid_sources[0x55]	15540	1			T32	2		T43	2		T64	1
valid_sources[0x56]	15958	1			T64	2		T44	1		T65	2
valid_sources[0x57]	14840	1			T32	1		T43	2		T64	2
valid_sources[0x58]	17185	1			T29	1		T44	2		T65	2
valid_sources[0x59]	16118	1			T4	1		T31	2		T43	1
valid_sources[0x5a]	17376	1			T43	1		T64	2		T44	4
valid_sources[0x5b]	15164	1			T32	2		T43	2		T64	1
valid_sources[0x5c]	16840	1			T29	1		T32	2		T43	3
valid_sources[0x5d]	15948	1			T29	1		T31	1		T32	1
valid_sources[0x5e]	14636	1			T32	1		T43	1		T44	2
valid_sources[0x5f]	15053	1			T32	2		T33	1		T64	6
valid_sources[0x60]	15982	1			T4	1		T29	4		T32	1
valid_sources[0x61]	16800	1			T29	3		T32	1		T64	2
valid_sources[0x62]	14439	1			T29	1		T32	3		T42	2
valid_sources[0x63]	16191	1			T29	3		T31	2		T43	1
valid_sources[0x64]	15622	1			T29	2		T32	1		T43	1
valid_sources[0x65]	15590	1			T29	4		T31	1		T32	1
valid_sources[0x66]	15402	1			T4	4		T32	3		T43	2
valid_sources[0x67]	15493	1			T4	1		T29	1		T32	2
valid_sources[0x68]	15615	1			T29	1		T43	2		T64	2
valid_sources[0x69]	16793	1			T32	1		T64	2		T44	5
valid_sources[0x6a]	14380	1			T43	2		T64	1		T44	9
valid_sources[0x6b]	15130	1			T29	1		T31	4		T32	5
valid_sources[0x6c]	16641	1			T31	1		T32	2		T64	2
valid_sources[0x6d]	15731	1			T28	2		T31	2		T43	3
valid_sources[0x6e]	15380	1			T29	1		T31	1		T64	2
valid_sources[0x6f]	16581	1			T29	1		T43	1		T64	4
valid_sources[0x70]	14204	1			T24	1		T28	8		T29	1
valid_sources[0x71]	15061	1			T24	1		T31	11		T32	1
valid_sources[0x72]	17181	1			T32	1		T43	1		T64	2
valid_sources[0x73]	15858	1			T24	1		T29	1		T31	2
valid_sources[0x74]	15011	1			T43	3		T64	4		T65	1
valid_sources[0x75]	16241	1			T29	1		T32	1		T42	4
valid_sources[0x76]	16083	1			T32	2		T43	1		T64	2
valid_sources[0x77]	15974	1			T6	1		T29	1		T32	1
valid_sources[0x78]	15540	1			T29	1		T31	1		T64	1
valid_sources[0x79]	17348	1			T32	1		T43	4		T64	2
valid_sources[0x7a]	18604	1			T29	1		T31	4		T32	2
valid_sources[0x7b]	16952	1			T29	2		T43	2		T64	5
valid_sources[0x7c]	17644	1			T31	2		T43	2		T64	2
valid_sources[0x7d]	17049	1			T29	2		T31	1		T65	2
valid_sources[0x7e]	18060	1			T29	2		T31	1		T32	1
valid_sources[0x7f]	15470	1			T31	1		T32	2		T43	2
valid_sources[0x80]	15858	1			T4	2		T29	2		T31	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

876460

1

T4

3

T28

35

T29

113

values[0x0]

all_enables

biggest_size

1322485

1

T6

1

T4

29

T7

5

values[0x1]

all_enables

biggest_size

1276078

1

T4

21

T7

2

T24

1