Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Unreachable
1	0	Covered	T1,T22,T38

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	161479837	159139597	0	0
AllClkBypReqTrue_A	161479837	147285	0	0
IoClkBypReqFalse_A	161479837	159053024	0	2412
IoClkBypReqTrue_A	161479837	229410	0	0
LcClkBypAckFalse_A	161479837	159152577	0	0
LcClkBypAckTrue_A	161479837	134305	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161479837	159139597	0	0
T1	198814	198333	0	0
T4	71335	71170	0	0
T5	193779	193594	0	0
T6	966	917	0	0
T7	1045	972	0	0
T16	1543	1379	0	0
T17	36567	36505	0	0
T18	2743	2182	0	0
T19	2542	2140	0	0
T24	742	694	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161479837	147285	0	0
T1	198814	2510	0	0
T3	0	530	0	0
T5	193779	0	0	0
T16	1543	0	0	0
T17	36567	0	0	0
T18	2743	384	0	0
T19	2542	307	0	0
T20	2242	378	0	0
T21	1396	0	0	0
T22	1419	0	0	0
T23	232376	0	0	0
T105	0	38	0	0
T106	0	26	0	0
T107	0	68	0	0
T108	0	138	0	0
T109	0	211	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161479837	159053024	0	2412
T1	198814	198245	0	3
T4	71335	71168	0	3
T5	193779	193592	0	3
T6	966	915	0	3
T7	1045	970	0	3
T16	1543	1377	0	3
T17	36567	36503	0	3
T18	2743	1951	0	3
T19	2542	1941	0	3
T24	742	692	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161479837	229410	0	0
T1	198814	3381	0	0
T3	0	834	0	0
T5	193779	0	0	0
T16	1543	0	0	0
T17	36567	0	0	0
T18	2743	613	0	0
T19	2542	504	0	0
T20	2242	363	0	0
T21	1396	0	0	0
T22	1419	0	0	0
T23	232376	0	0	0
T105	0	34	0	0
T106	0	513	0	0
T107	0	123	0	0
T108	0	244	0	0
T110	0	21	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161479837	159152577	0	0
T1	198814	198388	0	0
T4	71335	71170	0	0
T5	193779	193594	0	0
T6	966	917	0	0
T7	1045	972	0	0
T16	1543	1379	0	0
T17	36567	36505	0	0
T18	2743	2156	0	0
T19	2542	2203	0	0
T24	742	694	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161479837	134305	0	0
T1	198814	1968	0	0
T3	0	385	0	0
T5	193779	0	0	0
T16	1543	0	0	0
T17	36567	0	0	0
T18	2743	410	0	0
T19	2542	244	0	0
T20	2242	238	0	0
T21	1396	0	0	0
T22	1419	0	0	0
T23	232376	0	0	0
T105	0	30	0	0
T106	0	251	0	0
T107	0	75	0	0
T108	0	157	0	0
T110	0	17	0	0