Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1981470104	16030	0	0
TransStop_A	1981470104	8143	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1981470104	16030	0	0
T1	2032796	140	0	0
T3	0	114	0	0
T5	727120	0	0	0
T9	0	80	0	0
T16	6432	0	0	0
T17	274508	0	0	0
T18	11432	0	0	0
T19	10484	0	0	0
T20	35896	0	0	0
T21	111752	17	0	0
T22	37876	0	0	0
T23	824272	0	0	0
T38	0	4	0	0
T111	0	4	0	0
T112	0	40	0	0
T113	0	17	0	0
T114	0	4	0	0
T115	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1981470104	8143	0	0
T1	2032796	71	0	0
T3	0	54	0	0
T5	727120	0	0	0
T9	0	47	0	0
T10	0	33	0	0
T16	6432	0	0	0
T17	274508	0	0	0
T18	11432	0	0	0
T19	10484	0	0	0
T20	35896	0	0	0
T21	111752	5	0	0
T22	37876	0	0	0
T23	824272	0	0	0
T38	0	4	0	0
T111	0	4	0	0
T112	0	19	0	0
T113	0	13	0	0
T114	0	4	0	0
T115	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	495367526	4019	0	0
TransStop_A	495367526	2032	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367526	4019	0	0
T1	508199	38	0	0
T3	0	28	0	0
T5	181780	0	0	0
T9	0	21	0	0
T16	1608	0	0	0
T17	68627	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8974	0	0	0
T21	27938	3	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T111	0	1	0	0
T112	0	9	0	0
T113	0	4	0	0
T114	0	1	0	0
T115	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367526	2032	0	0
T1	508199	21	0	0
T3	0	13	0	0
T5	181780	0	0	0
T9	0	12	0	0
T10	0	33	0	0
T16	1608	0	0	0
T17	68627	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8974	0	0	0
T21	27938	0	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T111	0	1	0	0
T112	0	5	0	0
T113	0	3	0	0
T114	0	1	0	0
T115	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	495367526	3989	0	0
TransStop_A	495367526	2031	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367526	3989	0	0
T1	508199	29	0	0
T3	0	27	0	0
T5	181780	0	0	0
T9	0	19	0	0
T16	1608	0	0	0
T17	68627	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8974	0	0	0
T21	27938	3	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T111	0	1	0	0
T112	0	11	0	0
T113	0	3	0	0
T114	0	1	0	0
T115	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367526	2031	0	0
T1	508199	14	0	0
T3	0	13	0	0
T5	181780	0	0	0
T9	0	12	0	0
T16	1608	0	0	0
T17	68627	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8974	0	0	0
T21	27938	1	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T111	0	1	0	0
T112	0	7	0	0
T113	0	2	0	0
T114	0	1	0	0
T115	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	495367526	3986	0	0
TransStop_A	495367526	2031	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367526	3986	0	0
T1	508199	37	0	0
T3	0	26	0	0
T5	181780	0	0	0
T9	0	21	0	0
T16	1608	0	0	0
T17	68627	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8974	0	0	0
T21	27938	6	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T111	0	1	0	0
T112	0	9	0	0
T113	0	4	0	0
T114	0	1	0	0
T115	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367526	2031	0	0
T1	508199	20	0	0
T3	0	11	0	0
T5	181780	0	0	0
T9	0	13	0	0
T16	1608	0	0	0
T17	68627	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8974	0	0	0
T21	27938	2	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T111	0	1	0	0
T112	0	3	0	0
T113	0	4	0	0
T114	0	1	0	0
T115	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	495367526	4036	0	0
TransStop_A	495367526	2049	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367526	4036	0	0
T1	508199	36	0	0
T3	0	33	0	0
T5	181780	0	0	0
T9	0	19	0	0
T16	1608	0	0	0
T17	68627	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8974	0	0	0
T21	27938	5	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T111	0	1	0	0
T112	0	11	0	0
T113	0	6	0	0
T114	0	1	0	0
T115	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367526	2049	0	0
T1	508199	16	0	0
T3	0	17	0	0
T5	181780	0	0	0
T9	0	10	0	0
T16	1608	0	0	0
T17	68627	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8974	0	0	0
T21	27938	2	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T111	0	1	0	0
T112	0	4	0	0
T113	0	4	0	0
T114	0	1	0	0
T115	0	1	0	0