Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	161479837	15505786	0	59

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161479837	15505786	0	59
T1	198814	84489	0	0
T2	0	49100	0	1
T3	0	13730	0	0
T5	193779	0	0	0
T9	0	4794	0	1
T10	0	219202	0	0
T11	0	12518	0	1
T12	0	325701	0	0
T13	0	44197	0	0
T14	0	4328	0	1
T15	0	0	0	1
T16	1543	0	0	0
T17	36567	0	0	0
T18	2743	0	0	0
T19	2542	0	0	0
T20	2242	0	0	0
T21	1396	0	0	0
T22	1419	0	0	0
T23	232376	0	0	0
T25	0	1002	0	1
T26	0	0	0	1
T116	0	0	0	1
T117	0	0	0	1
T118	0	0	0	1