Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	162395068	5092698	0	0
clk_enables_rd_A	162395068	45642	0	0
clk_hints_rd_A	162395068	40532	0	0
extclk_ctrl_rd_A	162395068	51275	0	0
extclk_ctrl_regwen_rd_A	162395068	39387	0	0
jitter_enable_rd_A	162395068	56618	0	0
jitter_regwen_rd_A	162395068	43738	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162395068	5092698	0	0
T28	6427	484	0	0
T31	1392	34	0	0
T45	14159	3	0	0
T66	13279	1191	0	0
T69	3591	0	0	0
T71	4324	0	0	0
T73	1988	25	0	0
T74	0	8	0	0
T75	0	49	0	0
T78	1487	20	0	0
T79	1333	0	0	0
T80	816	0	0	0
T82	0	3	0	0
T126	0	9	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162395068	45642	0	0
T28	6427	2	0	0
T42	1256	1	0	0
T44	9314	54	0	0
T65	7378	59	0	0
T66	13279	4	0	0
T68	0	36	0	0
T69	3591	0	0	0
T73	1988	19	0	0
T78	1487	6	0	0
T79	1333	0	0	0
T80	816	0	0	0
T89	0	2	0	0
T126	0	1	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162395068	40532	0	0
T28	6427	13	0	0
T42	1256	3	0	0
T44	9314	76	0	0
T65	7378	43	0	0
T66	13279	2	0	0
T68	0	17	0	0
T69	3591	0	0	0
T73	1988	4	0	0
T78	1487	7	0	0
T79	1333	0	0	0
T80	816	0	0	0
T89	0	4	0	0
T126	0	9	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162395068	51275	0	0
T28	6427	1	0	0
T46	2590	0	0	0
T65	7378	50	0	0
T66	13279	17	0	0
T68	5279	24	0	0
T69	3591	0	0	0
T73	1988	2	0	0
T78	1487	2	0	0
T79	1333	0	0	0
T80	816	0	0	0
T126	0	3	0	0
T128	0	11	0	0
T137	0	45	0	0
T138	0	1	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162395068	39387	0	0
T28	6427	2	0	0
T42	1256	10	0	0
T44	9314	47	0	0
T65	7378	59	0	0
T66	13279	3	0	0
T68	0	27	0	0
T69	3591	0	0	0
T73	1988	0	0	0
T78	1487	8	0	0
T79	1333	0	0	0
T80	816	0	0	0
T126	0	2	0	0
T137	0	13	0	0
T139	0	8	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162395068	56618	0	0
T42	1256	7	0	0
T44	9314	29	0	0
T46	2590	0	0	0
T65	7378	46	0	0
T66	13279	8	0	0
T68	0	27	0	0
T69	3591	0	0	0
T73	1988	9	0	0
T78	1487	4	0	0
T79	1333	0	0	0
T80	816	0	0	0
T137	0	2	0	0
T138	0	6	0	0
T139	0	7	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162395068	43738	0	0
T28	6427	2	0	0
T44	9314	21	0	0
T46	2590	0	0	0
T65	7378	56	0	0
T66	13279	8	0	0
T68	0	25	0	0
T69	3591	0	0	0
T73	1988	5	0	0
T78	1487	8	0	0
T79	1333	0	0	0
T80	816	0	0	0
T89	0	6	0	0
T137	0	27	0	0
T139	0	3	0	0