Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T38
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47702	0	0
CgEnOn_A	2147483647	38814	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47702	0	0
T1	1319928	459	0	0
T4	83153	3	0	0
T5	426652	3	0	0
T6	3261	8	0	0
T7	3678	22	0	0
T10	0	5	0	0
T16	4278	3	0	0
T17	163738	3	0	0
T18	7967	3	0	0
T19	7194	3	0	0
T20	8973	0	0	0
T21	0	3	0	0
T24	5838	3	0	0
T39	2781	13	0	0
T40	3289	25	0	0
T41	0	15	0	0
T62	123555	0	0	0
T106	30664	0	0	0
T110	9820	0	0	0
T111	8256	0	0	0
T112	30507	0	0	0
T119	7925	0	0	0
T140	0	5	0	0
T141	0	20	0	0
T142	0	5	0	0
T143	0	25	0	0
T144	0	20	0	0
T145	0	5	0	0
T147	8532	0	0	0
T148	16809	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38814	0	0
T1	1319928	441	0	0
T3	0	127	0	0
T4	83153	0	0	0
T5	426652	0	0	0
T6	3261	5	0	0
T7	3678	19	0	0
T10	0	4	0	0
T16	4278	0	0	0
T17	163738	0	0	0
T18	7967	0	0	0
T19	7194	0	0	0
T20	8973	0	0	0
T21	0	3	0	0
T24	5838	0	0	0
T38	0	92	0	0
T39	2781	19	0	0
T40	3289	37	0	0
T41	0	15	0	0
T62	123555	0	0	0
T106	30664	0	0	0
T110	9820	0	0	0
T111	8256	4	0	0
T112	30507	9	0	0
T114	0	4	0	0
T119	7925	0	0	0
T140	0	5	0	0
T141	0	20	0	0
T142	0	5	0	0
T143	0	25	0	0
T144	0	20	0	0
T145	0	5	0	0
T146	0	4	0	0
T147	8532	43	0	0
T148	16809	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T38
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	231778285	149	0	0
CgEnOn_A	231778285	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231778285	149	0	0
T10	0	1	0	0
T39	607	2	0	0
T40	723	4	0	0
T41	0	3	0	0
T62	25726	0	0	0
T106	7205	0	0	0
T110	2172	0	0	0
T111	1820	0	0	0
T112	6753	0	0	0
T119	1897	0	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	1	0	0
T147	1881	0	0	0
T148	3897	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231778285	149	0	0
T10	0	1	0	0
T39	607	2	0	0
T40	723	4	0	0
T41	0	3	0	0
T62	25726	0	0	0
T106	7205	0	0	0
T110	2172	0	0	0
T111	1820	0	0	0
T112	6753	0	0	0
T119	1897	0	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	1	0	0
T147	1881	0	0	0
T148	3897	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T38
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115888420	149	0	0
CgEnOn_A	115888420	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115888420	149	0	0
T10	0	1	0	0
T39	303	2	0	0
T40	361	4	0	0
T41	0	3	0	0
T62	12864	0	0	0
T106	3601	0	0	0
T110	1085	0	0	0
T111	910	0	0	0
T112	3376	0	0	0
T119	946	0	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	1	0	0
T147	941	0	0	0
T148	1948	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115888420	149	0	0
T10	0	1	0	0
T39	303	2	0	0
T40	361	4	0	0
T41	0	3	0	0
T62	12864	0	0	0
T106	3601	0	0	0
T110	1085	0	0	0
T111	910	0	0	0
T112	3376	0	0	0
T119	946	0	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	1	0	0
T147	941	0	0	0
T148	1948	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T38
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	464905655	149	0	0
CgEnOn_A	464905655	145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464905655	149	0	0
T10	0	1	0	0
T39	1265	2	0	0
T40	1483	4	0	0
T41	0	3	0	0
T62	59237	0	0	0
T106	12656	0	0	0
T110	4393	0	0	0
T111	3706	0	0	0
T112	13626	0	0	0
T119	3190	0	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	1	0	0
T147	3828	0	0	0
T148	7068	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464905655	145	0	0
T39	1265	2	0	0
T40	1483	4	0	0
T41	0	3	0	0
T62	59237	0	0	0
T106	12656	0	0	0
T110	4393	0	0	0
T111	3706	0	0	0
T112	13626	0	0	0
T119	3190	0	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	4	0	0
T147	3828	0	0	0
T148	7068	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T38
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	495367080	159	0	0
CgEnOn_A	495367080	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367080	159	0	0
T39	1311	3	0	0
T40	1413	5	0	0
T41	0	4	0	0
T62	61708	0	0	0
T106	13184	0	0	0
T110	4576	0	0	0
T111	3861	0	0	0
T112	14194	0	0	0
T119	3323	0	0	0
T141	0	5	0	0
T142	0	3	0	0
T143	0	4	0	0
T144	0	5	0	0
T145	0	2	0	0
T146	0	7	0	0
T147	3987	0	0	0
T148	7363	0	0	0
T149	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367080	157	0	0
T39	1311	3	0	0
T40	1413	5	0	0
T41	0	4	0	0
T62	61708	0	0	0
T106	13184	0	0	0
T110	4576	0	0	0
T111	3861	0	0	0
T112	14194	0	0	0
T119	3323	0	0	0
T141	0	5	0	0
T142	0	3	0	0
T143	0	4	0	0
T144	0	5	0	0
T145	0	2	0	0
T146	0	7	0	0
T147	3987	0	0	0
T148	7363	0	0	0
T149	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T38
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115888420	149	0	0
CgEnOn_A	115888420	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115888420	149	0	0
T10	0	1	0	0
T39	303	2	0	0
T40	361	4	0	0
T41	0	3	0	0
T62	12864	0	0	0
T106	3601	0	0	0
T110	1085	0	0	0
T111	910	0	0	0
T112	3376	0	0	0
T119	946	0	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	1	0	0
T147	941	0	0	0
T148	1948	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115888420	149	0	0
T10	0	1	0	0
T39	303	2	0	0
T40	361	4	0	0
T41	0	3	0	0
T62	12864	0	0	0
T106	3601	0	0	0
T110	1085	0	0	0
T111	910	0	0	0
T112	3376	0	0	0
T119	946	0	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	1	0	0
T147	941	0	0	0
T148	1948	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T38
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	495367080	159	0	0
CgEnOn_A	495367080	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367080	159	0	0
T39	1311	3	0	0
T40	1413	5	0	0
T41	0	4	0	0
T62	61708	0	0	0
T106	13184	0	0	0
T110	4576	0	0	0
T111	3861	0	0	0
T112	14194	0	0	0
T119	3323	0	0	0
T141	0	5	0	0
T142	0	3	0	0
T143	0	4	0	0
T144	0	5	0	0
T145	0	2	0	0
T146	0	7	0	0
T147	3987	0	0	0
T148	7363	0	0	0
T149	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367080	157	0	0
T39	1311	3	0	0
T40	1413	5	0	0
T41	0	4	0	0
T62	61708	0	0	0
T106	13184	0	0	0
T110	4576	0	0	0
T111	3861	0	0	0
T112	14194	0	0	0
T119	3323	0	0	0
T141	0	5	0	0
T142	0	3	0	0
T143	0	4	0	0
T144	0	5	0	0
T145	0	2	0	0
T146	0	7	0	0
T147	3987	0	0	0
T148	7363	0	0	0
T149	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T38
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115888420	149	0	0
CgEnOn_A	115888420	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115888420	149	0	0
T10	0	1	0	0
T39	303	2	0	0
T40	361	4	0	0
T41	0	3	0	0
T62	12864	0	0	0
T106	3601	0	0	0
T110	1085	0	0	0
T111	910	0	0	0
T112	3376	0	0	0
T119	946	0	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	1	0	0
T147	941	0	0	0
T148	1948	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115888420	149	0	0
T10	0	1	0	0
T39	303	2	0	0
T40	361	4	0	0
T41	0	3	0	0
T62	12864	0	0	0
T106	3601	0	0	0
T110	1085	0	0	0
T111	910	0	0	0
T112	3376	0	0	0
T119	946	0	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	1	0	0
T147	941	0	0	0
T148	1948	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	231778285	7534	0	0
CgEnOn_A	231778285	5314	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231778285	7534	0	0
T1	232044	141	0	0
T4	23731	1	0	0
T5	69953	1	0	0
T6	913	3	0	0
T7	1028	7	0	0
T16	752	1	0	0
T17	27168	1	0	0
T18	1578	1	0	0
T19	1373	1	0	0
T24	1630	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231778285	5314	0	0
T1	232044	135	0	0
T3	0	34	0	0
T4	23731	0	0	0
T5	69953	0	0	0
T6	913	2	0	0
T7	1028	6	0	0
T16	752	0	0	0
T17	27168	0	0	0
T18	1578	0	0	0
T19	1373	0	0	0
T24	1630	0	0	0
T38	0	29	0	0
T39	0	2	0	0
T40	0	4	0	0
T111	0	1	0	0
T114	0	1	0	0
T147	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115888420	7195	0	0
CgEnOn_A	115888420	4976	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115888420	7195	0	0
T1	116021	139	0	0
T4	11866	1	0	0
T5	34976	1	0	0
T6	456	2	0	0
T7	514	6	0	0
T16	376	1	0	0
T17	13584	1	0	0
T18	788	1	0	0
T19	685	1	0	0
T24	815	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115888420	4976	0	0
T1	116021	133	0	0
T3	0	29	0	0
T4	11866	0	0	0
T5	34976	0	0	0
T6	456	1	0	0
T7	514	5	0	0
T16	376	0	0	0
T17	13584	0	0	0
T18	788	0	0	0
T19	685	0	0	0
T24	815	0	0	0
T38	0	27	0	0
T39	0	2	0	0
T40	0	4	0	0
T111	0	1	0	0
T114	0	1	0	0
T147	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	464905655	7664	0	0
CgEnOn_A	464905655	5441	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464905655	7664	0	0
T1	463664	141	0	0
T4	47556	1	0	0
T5	139944	1	0	0
T6	1892	3	0	0
T7	2136	9	0	0
T16	1543	1	0	0
T17	54360	1	0	0
T18	2743	1	0	0
T19	2515	1	0	0
T24	3393	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464905655	5441	0	0
T1	463664	135	0	0
T3	0	36	0	0
T4	47556	0	0	0
T5	139944	0	0	0
T6	1892	2	0	0
T7	2136	8	0	0
T16	1543	0	0	0
T17	54360	0	0	0
T18	2743	0	0	0
T19	2515	0	0	0
T24	3393	0	0	0
T38	0	35	0	0
T39	0	2	0	0
T40	0	4	0	0
T111	0	1	0	0
T114	0	1	0	0
T147	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	237638660	7580	0	0
CgEnOn_A	237638660	5360	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237638660	7580	0	0
T1	244515	139	0	0
T4	32419	1	0	0
T5	81495	1	0	0
T6	946	4	0	0
T7	1068	8	0	0
T16	772	1	0	0
T17	35821	1	0	0
T18	1371	1	0	0
T19	1257	1	0	0
T24	1697	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237638660	5360	0	0
T1	244515	133	0	0
T3	0	33	0	0
T4	32419	0	0	0
T5	81495	0	0	0
T6	946	3	0	0
T7	1068	7	0	0
T16	772	0	0	0
T17	35821	0	0	0
T18	1371	0	0	0
T19	1257	0	0	0
T24	1697	0	0	0
T38	0	32	0	0
T39	0	2	0	0
T40	0	4	0	0
T111	0	1	0	0
T114	0	1	0	0
T147	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T38
1	0	Covered	T1,T21,T38
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	495367080	4178	0	0
CgEnOn_A	495367080	4180	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367080	4178	0	0
T1	508199	38	0	0
T3	0	28	0	0
T5	181779	0	0	0
T16	1607	0	0	0
T17	68626	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8973	0	0	0
T21	27938	3	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T111	0	1	0	0
T112	0	9	0	0
T113	0	4	0	0
T114	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367080	4180	0	0
T1	508199	38	0	0
T3	0	28	0	0
T5	181779	0	0	0
T16	1607	0	0	0
T17	68626	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8973	0	0	0
T21	27938	3	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T111	0	1	0	0
T112	0	9	0	0
T113	0	4	0	0
T114	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T38
1	0	Covered	T1,T21,T38
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	495367080	4148	0	0
CgEnOn_A	495367080	4148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367080	4148	0	0
T1	508199	29	0	0
T3	0	27	0	0
T5	181779	0	0	0
T16	1607	0	0	0
T17	68626	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8973	0	0	0
T21	27938	3	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T111	0	1	0	0
T112	0	11	0	0
T113	0	3	0	0
T114	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367080	4148	0	0
T1	508199	29	0	0
T3	0	27	0	0
T5	181779	0	0	0
T16	1607	0	0	0
T17	68626	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8973	0	0	0
T21	27938	3	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T111	0	1	0	0
T112	0	11	0	0
T113	0	3	0	0
T114	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T38
1	0	Covered	T1,T21,T38
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	495367080	4145	0	0
CgEnOn_A	495367080	4145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367080	4145	0	0
T1	508199	37	0	0
T3	0	26	0	0
T5	181779	0	0	0
T16	1607	0	0	0
T17	68626	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8973	0	0	0
T21	27938	6	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T111	0	1	0	0
T112	0	9	0	0
T113	0	4	0	0
T114	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367080	4145	0	0
T1	508199	37	0	0
T3	0	26	0	0
T5	181779	0	0	0
T16	1607	0	0	0
T17	68626	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8973	0	0	0
T21	27938	6	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T111	0	1	0	0
T112	0	9	0	0
T113	0	4	0	0
T114	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T38
1	0	Covered	T1,T21,T38
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	495367080	4195	0	0
CgEnOn_A	495367080	4195	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367080	4195	0	0
T1	508199	36	0	0
T3	0	33	0	0
T5	181779	0	0	0
T16	1607	0	0	0
T17	68626	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8973	0	0	0
T21	27938	5	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T111	0	1	0	0
T112	0	11	0	0
T113	0	6	0	0
T114	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495367080	4195	0	0
T1	508199	36	0	0
T3	0	33	0	0
T5	181779	0	0	0
T16	1607	0	0	0
T17	68626	0	0	0
T18	2858	0	0	0
T19	2621	0	0	0
T20	8973	0	0	0
T21	27938	5	0	0
T22	9469	0	0	0
T23	206068	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T111	0	1	0	0
T112	0	11	0	0
T113	0	6	0	0
T114	0	1	0	0