Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	636165	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3757330

1

T5

167

T6

269

T31

283

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1078869	1			T5	39		T6	590		T31	594
values[0x0]	1520957	1			T5	56		T6	210		T31	211
values[0x1]	1793669	1			T5	87		T6	223		T31	216

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	346062	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4047433

1

T5

179

T6

524

T31

533

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16601	1			T5	2		T6	6		T31	1
valid_sources[0x01]	16812	1			T31	2		T36	1		T47	9
valid_sources[0x02]	16810	1			T31	10		T33	1		T74	2
valid_sources[0x03]	18199	1			T33	1		T37	4		T75	1
valid_sources[0x04]	17294	1			T6	2		T31	6		T33	1
valid_sources[0x05]	17957	1			T5	1		T31	2		T37	1
valid_sources[0x06]	17935	1			T31	2		T33	1		T36	1
valid_sources[0x07]	17106	1			T33	1		T37	1		T47	5
valid_sources[0x08]	17140	1			T31	4		T36	2		T47	6
valid_sources[0x09]	16949	1			T31	2		T33	7		T36	1
valid_sources[0x0a]	16490	1			T5	6		T36	1		T77	1
valid_sources[0x0b]	16301	1			T6	17		T33	4		T36	2
valid_sources[0x0c]	18150	1			T5	2		T6	5		T31	8
valid_sources[0x0d]	16574	1			T6	29		T31	3		T47	2
valid_sources[0x0e]	16023	1			T6	11		T31	6		T33	2
valid_sources[0x0f]	17029	1			T31	2		T36	4		T74	7
valid_sources[0x10]	16616	1			T31	6		T36	2		T74	5
valid_sources[0x11]	17500	1			T31	2		T33	1		T36	1
valid_sources[0x12]	17954	1			T31	6		T33	1		T75	1
valid_sources[0x13]	19249	1			T5	5		T31	12		T36	3
valid_sources[0x14]	17015	1			T31	7		T36	2		T74	3
valid_sources[0x15]	16697	1			T6	3		T31	1		T36	2
valid_sources[0x16]	18162	1			T5	1		T6	6		T31	3
valid_sources[0x17]	17759	1			T5	3		T33	2		T36	3
valid_sources[0x18]	16076	1			T5	1		T6	9		T31	3
valid_sources[0x19]	16781	1			T31	2		T37	1		T47	5
valid_sources[0x1a]	17372	1			T31	14		T36	4		T75	2
valid_sources[0x1b]	17307	1			T6	15		T31	4		T36	4
valid_sources[0x1c]	16251	1			T31	2		T36	1		T75	1
valid_sources[0x1d]	16944	1			T5	1		T36	1		T47	4
valid_sources[0x1e]	17487	1			T5	1		T6	3		T31	13
valid_sources[0x1f]	17213	1			T5	1		T6	7		T31	5
valid_sources[0x20]	17160	1			T5	1		T31	7		T36	1
valid_sources[0x21]	16584	1			T5	1		T6	7		T31	4
valid_sources[0x22]	17321	1			T5	2		T31	4		T36	1
valid_sources[0x23]	16613	1			T75	2		T47	10		T77	3
valid_sources[0x24]	18140	1			T6	4		T31	5		T36	3
valid_sources[0x25]	18037	1			T6	7		T31	3		T33	1
valid_sources[0x26]	17857	1			T36	6		T74	12		T47	2
valid_sources[0x27]	17078	1			T31	2		T36	3		T47	7
valid_sources[0x28]	16857	1			T6	4		T31	2		T33	2
valid_sources[0x29]	16753	1			T6	7		T31	3		T74	4
valid_sources[0x2a]	16721	1			T5	1		T31	5		T33	2
valid_sources[0x2b]	18501	1			T6	4		T31	7		T37	2
valid_sources[0x2c]	17910	1			T5	2		T6	14		T31	8
valid_sources[0x2d]	16876	1			T6	17		T31	4		T36	4
valid_sources[0x2e]	17362	1			T6	13		T31	3		T36	1
valid_sources[0x2f]	16408	1			T6	4		T31	2		T33	4
valid_sources[0x30]	16750	1			T5	1		T31	3		T47	5
valid_sources[0x31]	15877	1			T6	5		T31	5		T32	27
valid_sources[0x32]	16393	1			T5	4		T6	20		T31	10
valid_sources[0x33]	16738	1			T6	2		T31	3		T75	1
valid_sources[0x34]	17669	1			T31	3		T33	1		T75	2
valid_sources[0x35]	17992	1			T5	3		T6	16		T31	4
valid_sources[0x36]	17667	1			T5	1		T6	11		T31	1
valid_sources[0x37]	17530	1			T6	3		T31	5		T33	4
valid_sources[0x38]	17048	1			T31	4		T32	21		T33	4
valid_sources[0x39]	16830	1			T31	6		T36	3		T37	1
valid_sources[0x3a]	17343	1			T31	11		T36	2		T47	3
valid_sources[0x3b]	19223	1			T31	3		T36	3		T75	1
valid_sources[0x3c]	16709	1			T31	2		T33	2		T37	1
valid_sources[0x3d]	16977	1			T33	3		T74	2		T77	4
valid_sources[0x3e]	17675	1			T31	1		T33	3		T36	2
valid_sources[0x3f]	16358	1			T36	3		T47	4		T77	8
valid_sources[0x40]	17701	1			T5	12		T6	17		T31	2
valid_sources[0x41]	16832	1			T5	2		T31	5		T33	7
valid_sources[0x42]	17591	1			T6	10		T31	4		T33	1
valid_sources[0x43]	17467	1			T31	3		T47	2		T88	3
valid_sources[0x44]	18157	1			T31	9		T36	2		T47	7
valid_sources[0x45]	17122	1			T5	2		T31	5		T35	5
valid_sources[0x46]	15679	1			T31	2		T36	1		T37	2
valid_sources[0x47]	17438	1			T31	6		T33	2		T36	3
valid_sources[0x48]	16652	1			T31	6		T33	1		T36	1
valid_sources[0x49]	16198	1			T31	3		T33	2		T35	11
valid_sources[0x4a]	17807	1			T5	3		T6	6		T31	9
valid_sources[0x4b]	16341	1			T36	1		T75	1		T47	4
valid_sources[0x4c]	17750	1			T5	1		T6	4		T31	5
valid_sources[0x4d]	17329	1			T5	1		T31	4		T36	3
valid_sources[0x4e]	18499	1			T5	3		T31	2		T33	1
valid_sources[0x4f]	17642	1			T5	1		T31	5		T36	3
valid_sources[0x50]	17793	1			T31	10		T33	2		T35	5
valid_sources[0x51]	18268	1			T5	2		T31	2		T36	3
valid_sources[0x52]	17942	1			T6	4		T31	1		T32	27
valid_sources[0x53]	15844	1			T31	6		T36	2		T47	5
valid_sources[0x54]	17655	1			T5	1		T32	37		T33	1
valid_sources[0x55]	16844	1			T5	3		T31	6		T33	1
valid_sources[0x56]	16495	1			T31	3		T36	1		T74	4
valid_sources[0x57]	18414	1			T6	8		T31	16		T36	2
valid_sources[0x58]	17310	1			T6	21		T31	7		T33	1
valid_sources[0x59]	15867	1			T5	2		T6	5		T33	2
valid_sources[0x5a]	17048	1			T31	8		T36	2		T37	1
valid_sources[0x5b]	16612	1			T31	2		T36	1		T74	20
valid_sources[0x5c]	16461	1			T31	10		T76	18		T88	1
valid_sources[0x5d]	16823	1			T5	2		T31	1		T33	1
valid_sources[0x5e]	17554	1			T31	4		T33	1		T36	2
valid_sources[0x5f]	18014	1			T31	8		T36	1		T75	3
valid_sources[0x60]	16407	1			T5	1		T31	3		T37	1
valid_sources[0x61]	17852	1			T31	3		T33	1		T36	2
valid_sources[0x62]	19992	1			T5	1		T6	13		T33	1
valid_sources[0x63]	17447	1			T31	5		T36	3		T37	2
valid_sources[0x64]	16370	1			T6	20		T31	5		T47	4
valid_sources[0x65]	16871	1			T31	2		T47	2		T77	7
valid_sources[0x66]	16094	1			T5	1		T31	4		T33	3
valid_sources[0x67]	16286	1			T31	7		T33	1		T36	2
valid_sources[0x68]	16666	1			T5	1		T31	3		T75	1
valid_sources[0x69]	17650	1			T6	5		T31	5		T33	1
valid_sources[0x6a]	16938	1			T5	4		T6	6		T31	7
valid_sources[0x6b]	16851	1			T31	2		T33	3		T36	3
valid_sources[0x6c]	17695	1			T36	1		T37	1		T75	1
valid_sources[0x6d]	17107	1			T31	3		T36	1		T47	2
valid_sources[0x6e]	16057	1			T6	9		T31	3		T33	1
valid_sources[0x6f]	16061	1			T5	1		T6	25		T31	8
valid_sources[0x70]	16695	1			T5	3		T36	1		T37	1
valid_sources[0x71]	16103	1			T31	6		T35	3		T36	2
valid_sources[0x72]	16903	1			T31	1		T33	4		T36	2
valid_sources[0x73]	17035	1			T5	2		T31	1		T33	1
valid_sources[0x74]	16816	1			T5	1		T31	3		T33	1
valid_sources[0x75]	17720	1			T6	7		T31	4		T33	8
valid_sources[0x76]	17836	1			T6	6		T31	5		T36	2
valid_sources[0x77]	15269	1			T5	5		T6	8		T31	2
valid_sources[0x78]	16355	1			T6	16		T31	4		T35	7
valid_sources[0x79]	16056	1			T5	2		T6	26		T31	10
valid_sources[0x7a]	17391	1			T5	1		T31	1		T75	4
valid_sources[0x7b]	16584	1			T5	4		T6	20		T31	8
valid_sources[0x7c]	18269	1			T33	5		T36	1		T37	1
valid_sources[0x7d]	16448	1			T5	2		T33	4		T74	1
valid_sources[0x7e]	17486	1			T31	2		T75	1		T47	3
valid_sources[0x7f]	16048	1			T31	2		T36	1		T75	1
valid_sources[0x80]	16693	1			T31	6		T33	2		T36	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

948271

1

T5

37

T6

73

T31

67

values[0x0]

all_enables

biggest_size

1426993

1

T5

56

T6

117

T31

138

values[0x1]

all_enables

biggest_size

1382066

1

T5

74

T6

79

T31

78