Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	820540945	75619	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820540945	75619	0	0
T1	363965	203	0	0
T2	2169040	1304	0	0
T3	0	53	0	0
T4	1125120	0	0	0
T11	0	293	0	0
T12	0	242	0	0
T13	0	201	0	0
T14	0	95	0	0
T15	0	220	0	0
T16	0	1777	0	0
T17	0	225	0	0
T18	5970	0	0	0
T19	9670	0	0	0
T20	9285	0	0	0
T21	7385	0	0	0
T22	9090	0	0	0
T23	9155	0	0	0
T24	9710	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	164108189	10949	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164108189	10949	0	0
T1	72793	33	0	0
T2	433808	210	0	0
T3	0	9	0	0
T4	225024	0	0	0
T11	0	46	0	0
T12	0	48	0	0
T13	0	26	0	0
T14	0	12	0	0
T15	0	35	0	0
T16	0	259	0	0
T17	0	29	0	0
T18	1194	0	0	0
T19	1934	0	0	0
T20	1857	0	0	0
T21	1477	0	0	0
T22	1818	0	0	0
T23	1831	0	0	0
T24	1942	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	164108189	15194	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164108189	15194	0	0
T1	72793	41	0	0
T2	433808	264	0	0
T3	0	11	0	0
T4	225024	0	0	0
T11	0	59	0	0
T12	0	48	0	0
T13	0	41	0	0
T14	0	20	0	0
T15	0	44	0	0
T16	0	356	0	0
T17	0	47	0	0
T18	1194	0	0	0
T19	1934	0	0	0
T20	1857	0	0	0
T21	1477	0	0	0
T22	1818	0	0	0
T23	1831	0	0	0
T24	1942	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	164108189	23381	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164108189	23381	0	0
T1	72793	55	0	0
T2	433808	358	0	0
T3	0	14	0	0
T4	225024	0	0	0
T11	0	82	0	0
T12	0	50	0	0
T13	0	64	0	0
T14	0	32	0	0
T15	0	61	0	0
T16	0	545	0	0
T17	0	75	0	0
T18	1194	0	0	0
T19	1934	0	0	0
T20	1857	0	0	0
T21	1477	0	0	0
T22	1818	0	0	0
T23	1831	0	0	0
T24	1942	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	164108189	10924	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164108189	10924	0	0
T1	72793	33	0	0
T2	433808	208	0	0
T3	0	8	0	0
T4	225024	0	0	0
T11	0	46	0	0
T12	0	48	0	0
T13	0	29	0	0
T14	0	12	0	0
T15	0	35	0	0
T16	0	257	0	0
T17	0	29	0	0
T18	1194	0	0	0
T19	1934	0	0	0
T20	1857	0	0	0
T21	1477	0	0	0
T22	1818	0	0	0
T23	1831	0	0	0
T24	1942	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	164108189	15171	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164108189	15171	0	0
T1	72793	41	0	0
T2	433808	264	0	0
T3	0	11	0	0
T4	225024	0	0	0
T11	0	60	0	0
T12	0	48	0	0
T13	0	41	0	0
T14	0	19	0	0
T15	0	45	0	0
T16	0	360	0	0
T17	0	45	0	0
T18	1194	0	0	0
T19	1934	0	0	0
T20	1857	0	0	0
T21	1477	0	0	0
T22	1818	0	0	0
T23	1831	0	0	0
T24	1942	0	0	0