Unified Coverage Report :: Module :: clkmgr_reg_top

Module : clkmgr_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.58	100.00	98.31			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.64	98.39	95.43	100.00		97.91	96.48

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_fault	100.00	100.00
u_alert_test_recov_fault	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_clk_enables_clk_io_div2_peri_en	100.00	100.00	100.00			100.00
u_clk_enables_clk_io_div4_peri_en	100.00	100.00	100.00			100.00
u_clk_enables_clk_io_peri_en	100.00	100.00	100.00			100.00
u_clk_enables_clk_usb_peri_en	100.00	100.00	100.00			100.00
u_clk_hints_clk_main_aes_hint	100.00	100.00	100.00			100.00
u_clk_hints_clk_main_hmac_hint	100.00	100.00	100.00			100.00
u_clk_hints_clk_main_kmac_hint	100.00	100.00	100.00			100.00
u_clk_hints_clk_main_otbn_hint	100.00	100.00	100.00			100.00
u_clk_hints_status_clk_main_aes_val	92.59	77.78	100.00			100.00
u_clk_hints_status_clk_main_hmac_val	92.59	77.78	100.00			100.00
u_clk_hints_status_clk_main_kmac_val	92.59	77.78	100.00			100.00
u_clk_hints_status_clk_main_otbn_val	92.59	77.78	100.00			100.00
u_extclk_ctrl_hi_speed_sel	100.00	100.00	100.00			100.00
u_extclk_ctrl_regwen	100.00	100.00	100.00			100.00
u_extclk_ctrl_sel	100.00	100.00	100.00			100.00
u_extclk_status	100.00	100.00
u_fatal_err_code_idle_cnt	96.30	88.89	100.00			100.00
u_fatal_err_code_reg_intg	96.30	88.89	100.00			100.00
u_fatal_err_code_shadow_storage_err	96.30	88.89	100.00			100.00
u_io_div2_meas_ctrl_en	100.00	100.00	100.00			100.00
u_io_div2_meas_ctrl_en_cdc	89.66	96.24	80.88			91.53	90.00
u_io_div2_meas_ctrl_shadowed_cdc	98.39	100.00	93.55			100.00	100.00
u_io_div2_meas_ctrl_shadowed_hi	99.55	100.00	98.21			100.00	100.00
u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync	100.00	100.00				100.00
u_io_div2_meas_ctrl_shadowed_hi_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_io_div2_meas_ctrl_shadowed_lo	99.55	100.00	98.21			100.00	100.00
u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync	100.00	100.00				100.00
u_io_div2_meas_ctrl_shadowed_lo_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_io_div4_meas_ctrl_en	100.00	100.00	100.00			100.00
u_io_div4_meas_ctrl_en_cdc	92.36	97.74	86.76			94.92	90.00
u_io_div4_meas_ctrl_shadowed_cdc	98.39	100.00	93.55			100.00	100.00
u_io_div4_meas_ctrl_shadowed_hi	99.55	100.00	98.21			100.00	100.00
u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync	100.00	100.00				100.00
u_io_div4_meas_ctrl_shadowed_hi_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_io_div4_meas_ctrl_shadowed_lo	99.55	100.00	98.21			100.00	100.00
u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync	100.00	100.00				100.00
u_io_div4_meas_ctrl_shadowed_lo_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_io_meas_ctrl_en	100.00	100.00	100.00			100.00
u_io_meas_ctrl_en_cdc	89.66	96.24	80.88			91.53	90.00
u_io_meas_ctrl_shadowed_cdc	98.39	100.00	93.55			100.00	100.00
u_io_meas_ctrl_shadowed_hi	99.55	100.00	98.21			100.00	100.00
u_io_meas_ctrl_shadowed_hi_err_storage_sync	100.00	100.00				100.00
u_io_meas_ctrl_shadowed_hi_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_io_meas_ctrl_shadowed_lo	99.55	100.00	98.21			100.00	100.00
u_io_meas_ctrl_shadowed_lo_err_storage_sync	100.00	100.00				100.00
u_io_meas_ctrl_shadowed_lo_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_jitter_enable	100.00	100.00	100.00			100.00
u_jitter_regwen	100.00	100.00	100.00			100.00
u_main_meas_ctrl_en	100.00	100.00	100.00			100.00
u_main_meas_ctrl_en_cdc	89.66	96.24	80.88			91.53	90.00
u_main_meas_ctrl_shadowed_cdc	98.39	100.00	93.55			100.00	100.00
u_main_meas_ctrl_shadowed_hi	99.55	100.00	98.21			100.00	100.00
u_main_meas_ctrl_shadowed_hi_err_storage_sync	100.00	100.00				100.00
u_main_meas_ctrl_shadowed_hi_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_main_meas_ctrl_shadowed_lo	99.55	100.00	98.21			100.00	100.00
u_main_meas_ctrl_shadowed_lo_err_storage_sync	100.00	100.00				100.00
u_main_meas_ctrl_shadowed_lo_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_measure_ctrl_regwen	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_recov_err_code_io_div2_measure_err	100.00	100.00	100.00			100.00
u_recov_err_code_io_div2_timeout_err	100.00	100.00	100.00			100.00
u_recov_err_code_io_div4_measure_err	100.00	100.00	100.00			100.00
u_recov_err_code_io_div4_timeout_err	100.00	100.00	100.00			100.00
u_recov_err_code_io_measure_err	100.00	100.00	100.00			100.00
u_recov_err_code_io_timeout_err	100.00	100.00	100.00			100.00
u_recov_err_code_main_measure_err	100.00	100.00	100.00			100.00
u_recov_err_code_main_timeout_err	100.00	100.00	100.00			100.00
u_recov_err_code_shadow_update_err	97.22	100.00	91.67			100.00
u_recov_err_code_usb_measure_err	100.00	100.00	100.00			100.00
u_recov_err_code_usb_timeout_err	100.00	100.00	100.00			100.00
u_reg_if	98.98	97.14	98.80			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_usb_meas_ctrl_en	100.00	100.00	100.00			100.00
u_usb_meas_ctrl_en_cdc	89.66	96.24	80.88			91.53	90.00
u_usb_meas_ctrl_shadowed_cdc	98.39	100.00	93.55			100.00	100.00
u_usb_meas_ctrl_shadowed_hi	99.55	100.00	98.21			100.00	100.00
u_usb_meas_ctrl_shadowed_hi_err_storage_sync	100.00	100.00				100.00
u_usb_meas_ctrl_shadowed_hi_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_usb_meas_ctrl_shadowed_lo	99.55	100.00	98.21			100.00	100.00
u_usb_meas_ctrl_shadowed_lo_err_storage_sync	100.00	100.00				100.00
u_usb_meas_ctrl_shadowed_lo_err_update_sync	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : clkmgr_reg_top

	Line No.	Total	Covered	Percent
TOTAL		244	244	100.00
ALWAYS	85	4	4	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
ALWAYS	280	4	4	100.00
CONT_ASSIGN	310	1	1	100.00
ALWAYS	323	3	3	100.00
CONT_ASSIGN	352	1	1	100.00
ALWAYS	366	4	4	100.00
CONT_ASSIGN	396	1	1	100.00
ALWAYS	409	3	3	100.00
CONT_ASSIGN	438	1	1	100.00
ALWAYS	452	4	4	100.00
CONT_ASSIGN	482	1	1	100.00
ALWAYS	495	3	3	100.00
CONT_ASSIGN	524	1	1	100.00
ALWAYS	538	4	4	100.00
CONT_ASSIGN	568	1	1	100.00
ALWAYS	581	3	3	100.00
CONT_ASSIGN	610	1	1	100.00
ALWAYS	624	4	4	100.00
CONT_ASSIGN	654	1	1	100.00
ALWAYS	667	3	3	100.00
CONT_ASSIGN	696	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	768	1	1	100.00
CONT_ASSIGN	1256	1	1	100.00
CONT_ASSIGN	1259	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1413	1	1	100.00
CONT_ASSIGN	1416	1	1	100.00
CONT_ASSIGN	1448	1	1	100.00
CONT_ASSIGN	1571	1	1	100.00
CONT_ASSIGN	1574	1	1	100.00
CONT_ASSIGN	1606	1	1	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1732	1	1	100.00
CONT_ASSIGN	1764	1	1	100.00
CONT_ASSIGN	1887	1	1	100.00
CONT_ASSIGN	1890	1	1	100.00
CONT_ASSIGN	1921	1	1	100.00
ALWAYS	2427	23	23	100.00
CONT_ASSIGN	2452	1	1	100.00
ALWAYS	2456	1	1	100.00
CONT_ASSIGN	2482	1	1	100.00
CONT_ASSIGN	2484	1	1	100.00
CONT_ASSIGN	2486	1	1	100.00
CONT_ASSIGN	2487	1	1	100.00
CONT_ASSIGN	2489	1	1	100.00
CONT_ASSIGN	2490	1	1	100.00
CONT_ASSIGN	2492	1	1	100.00
CONT_ASSIGN	2494	1	1	100.00
CONT_ASSIGN	2495	1	1	100.00
CONT_ASSIGN	2496	1	1	100.00
CONT_ASSIGN	2498	1	1	100.00
CONT_ASSIGN	2499	1	1	100.00
CONT_ASSIGN	2501	1	1	100.00
CONT_ASSIGN	2502	1	1	100.00
CONT_ASSIGN	2504	1	1	100.00
CONT_ASSIGN	2506	1	1	100.00
CONT_ASSIGN	2508	1	1	100.00
CONT_ASSIGN	2510	1	1	100.00
CONT_ASSIGN	2511	1	1	100.00
CONT_ASSIGN	2513	1	1	100.00
CONT_ASSIGN	2515	1	1	100.00
CONT_ASSIGN	2517	1	1	100.00
CONT_ASSIGN	2519	1	1	100.00
CONT_ASSIGN	2520	1	1	100.00
CONT_ASSIGN	2522	1	1	100.00
CONT_ASSIGN	2523	1	1	100.00
CONT_ASSIGN	2525	1	1	100.00
CONT_ASSIGN	2526	1	1	100.00
CONT_ASSIGN	2529	1	1	100.00
CONT_ASSIGN	2531	1	1	100.00
CONT_ASSIGN	2532	1	1	100.00
CONT_ASSIGN	2535	1	1	100.00
CONT_ASSIGN	2537	1	1	100.00
CONT_ASSIGN	2538	1	1	100.00
CONT_ASSIGN	2541	1	1	100.00
CONT_ASSIGN	2543	1	1	100.00
CONT_ASSIGN	2544	1	1	100.00
CONT_ASSIGN	2547	1	1	100.00
CONT_ASSIGN	2549	1	1	100.00
CONT_ASSIGN	2550	1	1	100.00
CONT_ASSIGN	2553	1	1	100.00
CONT_ASSIGN	2555	1	1	100.00
CONT_ASSIGN	2557	1	1	100.00
CONT_ASSIGN	2559	1	1	100.00
CONT_ASSIGN	2561	1	1	100.00
CONT_ASSIGN	2563	1	1	100.00
CONT_ASSIGN	2565	1	1	100.00
CONT_ASSIGN	2567	1	1	100.00
CONT_ASSIGN	2569	1	1	100.00
CONT_ASSIGN	2571	1	1	100.00
CONT_ASSIGN	2573	1	1	100.00
CONT_ASSIGN	2575	1	1	100.00
ALWAYS	2579	23	23	100.00
ALWAYS	2606	47	47	100.00
ALWAYS	2720	3	3	100.00
ALWAYS	2728	3	3	100.00
CONT_ASSIGN	2736	1	1	100.00
CONT_ASSIGN	2739	1	1	100.00
CONT_ASSIGN	2751	1	1	100.00
CONT_ASSIGN	2766	1	1	100.00
ALWAYS	2768	12	12	100.00
CONT_ASSIGN	2813	1	1	100.00
CONT_ASSIGN	2814	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv' or '../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
86	1	1
87	1	1
88	1	1
			MISSING_ELSE
94	1	1
106	1	1
107	1	1
135	1	1
136	1	1
280	1	1
281	1	1
282	1	1
283	1	1
310	1	1
323	1	1
324	1	1
325	1	1
352	1	1
366	1	1
367	1	1
368	1	1
369	1	1
396	1	1
409	1	1
410	1	1
411	1	1
438	1	1
452	1	1
453	1	1
454	1	1
455	1	1
482	1	1
495	1	1
496	1	1
497	1	1
524	1	1
538	1	1
539	1	1
540	1	1
541	1	1
568	1	1
581	1	1
582	1	1
583	1	1
610	1	1
624	1	1
625	1	1
626	1	1
627	1	1
654	1	1
667	1	1
668	1	1
669	1	1
696	1	1
703	1	1
718	1	1
734	1	1
768	1	1
1256	1	1
1259	1	1
1290	1	1
1413	1	1
1416	1	1
1448	1	1
1571	1	1
1574	1	1
1606	1	1
1729	1	1
1732	1	1
1764	1	1
1887	1	1
1890	1	1
1921	1	1
2427	1	1
2428	1	1
2429	1	1
2430	1	1
2431	1	1
2432	1	1
2433	1	1
2434	1	1
2435	1	1
2436	1	1
2437	1	1
2438	1	1
2439	1	1
2440	1	1
2441	1	1
2442	1	1
2443	1	1
2444	1	1
2445	1	1
2446	1	1
2447	1	1
2448	1	1
2449	1	1
2452	1	1
2456	1	1
2482	1	1
2484	1	1
2486	1	1
2487	1	1
2489	1	1
2490	1	1
2492	1	1
2494	1	1
2495	1	1
2496	1	1
2498	1	1
2499	1	1
2501	1	1
2502	1	1
2504	1	1
2506	1	1
2508	1	1
2510	1	1
2511	1	1
2513	1	1
2515	1	1
2517	1	1
2519	1	1
2520	1	1
2522	1	1
2523	1	1
2525	1	1
2526	1	1
2529	1	1
2531	1	1
2532	1	1
2535	1	1
2537	1	1
2538	1	1
2541	1	1
2543	1	1
2544	1	1
2547	1	1
2549	1	1
2550	1	1
2553	1	1
2555	1	1
2557	1	1
2559	1	1
2561	1	1
2563	1	1
2565	1	1
2567	1	1
2569	1	1
2571	1	1
2573	1	1
2575	1	1
2579	1	1
2580	1	1
2581	1	1
2582	1	1
2583	1	1
2584	1	1
2585	1	1
2586	1	1
2587	1	1
2588	1	1
2589	1	1
2590	1	1
2591	1	1
2592	1	1
2593	1	1
2594	1	1
2595	1	1
2596	1	1
2597	1	1
2598	1	1
2599	1	1
2600	1	1
2601	1	1
2606	1	1
2607	1	1
2609	1	1
2610	1	1
2614	1	1
2618	1	1
2619	1	1
2623	1	1
2627	1	1
2631	1	1
2635	1	1
2636	1	1
2637	1	1
2638	1	1
2642	1	1
2643	1	1
2644	1	1
2645	1	1
2649	1	1
2650	1	1
2651	1	1
2652	1	1
2656	1	1
2660	1	1
2663	1	1
2666	1	1
2669	1	1
2672	1	1
2675	1	1
2678	1	1
2681	1	1
2684	1	1
2687	1	1
2690	1	1
2691	1	1
2692	1	1
2693	1	1
2694	1	1
2695	1	1
2696	1	1
2697	1	1
2698	1	1
2699	1	1
2700	1	1
2704	1	1
2705	1	1
2706	1	1
2720	1	1
2721	1	1
2723	1	1
2728	1	1
2729	1	1
2731	1	1
2736	1	1
2739	1	1
2751	1	1
2766	1	1
2768	1	1
2769	1	1
2771	1	1
2774	1	1
2777	1	1
2780	1	1
2783	1	1
2786	1	1
2789	1	1
2792	1	1
2795	1	1
2798	1	1
2813	1	1
2814	1	1

---

Cond Coverage for Module : clkmgr_reg_top

	Total	Covered	Percent
Conditions	296	291	98.31
Logical	296	291	98.31
Non-Logical	0	0
Event	0	0

 LINE       75
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       87
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T56,T57,T66
1	0	Covered	T6,T31,T47

 LINE       94
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T5,T6,T7
0	0	1	Covered	T56,T57,T66
0	1	0	Covered	T6,T31,T47
1	0	0	Covered	T6,T31,T47

 LINE       136
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T5,T6,T7
0	0	1	Covered	T6,T31,T47
0	1	0	Covered	T5,T36,T81
1	0	0	Covered	T5,T36,T81

 LINE       136
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T31

 LINE       768
 EXPRESSION (extclk_ctrl_we & extclk_ctrl_regwen_qs)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T30,T102,T103
1	1	Covered	T2,T19,T20

 LINE       1259
 EXPRESSION (io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T102,T103
1	1	Covered	T1,T2,T4

 LINE       1290
 EXPRESSION (io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen)
             -------------1-------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T31,T32
1	0	Covered	T6,T31,T35
1	1	Covered	T6,T31,T32

 LINE       1416
 EXPRESSION (io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T102,T103
1	1	Covered	T1,T2,T4

 LINE       1448
 EXPRESSION (io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T31,T32
1	0	Covered	T6,T31,T35
1	1	Covered	T6,T31,T32

 LINE       1574
 EXPRESSION (io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T102,T103
1	1	Covered	T1,T2,T4

 LINE       1606
 EXPRESSION (io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T31,T32
1	0	Covered	T6,T31,T35
1	1	Covered	T6,T31,T32

 LINE       1732
 EXPRESSION (main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T102,T103
1	1	Covered	T1,T2,T4

 LINE       1764
 EXPRESSION (main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen)
             ---------------1---------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T31,T32
1	0	Covered	T6,T31,T47
1	1	Covered	T6,T31,T33

 LINE       1890
 EXPRESSION (usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen)
             -----------1-----------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T102,T103
1	1	Covered	T1,T2,T4

 LINE       1921
 EXPRESSION (usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T31,T32
1	0	Covered	T6,T31,T35
1	1	Covered	T6,T31,T32

 LINE       2428
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2429
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2430
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T31,T32

 LINE       2431
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_STATUS_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2432
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_REGWEN_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2433
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_ENABLE_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2434
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_ENABLES_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2435
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2436
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_STATUS_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2437
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MEASURE_CTRL_REGWEN_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2438
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_EN_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T31,T32

 LINE       2439
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2440
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T31,T32

 LINE       2441
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2442
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T31,T32

 LINE       2443
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2444
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2445
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2446
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_EN_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T31,T32

 LINE       2447
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2448
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_RECOV_ERR_CODE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2449
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_FATAL_ERR_CODE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2452
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T31

 LINE       2452
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31

 LINE       2456
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T5,T6,T31
22 (addr_hit[21] & ((|(4'...	Covered	T5,T6,T31
21 (addr_hit[20] & ((|(4'...	Covered	T5,T6,T31
20 (addr_hit[19] & ((|(4'...	Covered	T5,T6,T31
19 (addr_hit[18] & ((|(4'...	Covered	T5,T31,T32
18 (addr_hit[17] & ((|(4'...	Covered	T5,T6,T31
17 (addr_hit[16] & ((|(4'...	Covered	T5,T6,T31
16 (addr_hit[15] & ((|(4'...	Covered	T5,T6,T31
15 (addr_hit[14] & ((|(4'...	Covered	T5,T31,T32
14 (addr_hit[13] & ((|(4'...	Covered	T5,T6,T31
13 (addr_hit[12] & ((|(4'...	Covered	T5,T31,T32
12 (addr_hit[11] & ((|(4'...	Covered	T5,T6,T31
11 (addr_hit[10] & ((|(4'...	Covered	T5,T31,T32
10 (addr_hit[9] & ((|(4'b...	Covered	T5,T6,T31
9 (addr_hit[8] & ((|(4'b...	Covered	T5,T6,T31
8 (addr_hit[7] & ((|(4'b...	Covered	T5,T6,T31
7 (addr_hit[6] & ((|(4'b...	Covered	T5,T6,T31
6 (addr_hit[5] & ((|(4'b...	Covered	T5,T6,T31
5 (addr_hit[4] & ((|(4'b...	Covered	T5,T6,T31
4 (addr_hit[3] & ((|(4'b...	Covered	T5,T6,T31
3 (addr_hit[2] & ((|(4'b...	Covered	T5,T31,T32
2 (addr_hit[1] & ((|(4'b...	Covered	T5,T6,T31
1 (addr_hit[0] & ((|(4'b...	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T31,T32
1	1	Covered	T5,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T31,T32
1	1	Covered	T5,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T31,T32
1	1	Covered	T5,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T31,T32
1	1	Covered	T5,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T31,T32
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T31,T32
1	1	Covered	T5,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2482
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T31,T36,T49
1	1	1	Covered	T6,T31,T35

 LINE       2487
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T5,T31,T36
1	1	1	Covered	T6,T31,T35

 LINE       2490
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T31,T32
1	1	0	Covered	T5,T36,T82
1	1	1	Covered	T2,T19,T20

 LINE       2495
 EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T83,T104,T105
1	1	1	Covered	T6,T31,T32

 LINE       2496
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T36,T84,T86
1	1	1	Covered	T6,T31,T35

 LINE       2499
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T5,T6,T36
1	1	1	Covered	T6,T31,T35

 LINE       2502
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T5,T36,T49
1	1	1	Covered	T6,T31,T35

 LINE       2511
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T5,T6,T36
1	1	1	Covered	T6,T31,T35

 LINE       2520
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T36,T81,T82
1	1	1	Covered	T6,T31,T35

 LINE       2523
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T31,T32
1	1	0	Covered	T36,T47,T49
1	1	1	Covered	T1,T2,T4

 LINE       2525
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T6,T106
1	1	1	Covered	T6,T31,T32

 LINE       2526
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T5,T36,T47
1	1	1	Covered	T6,T31,T32

 LINE       2529
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T31,T32
1	1	0	Covered	T49,T82,T84
1	1	1	Covered	T1,T2,T4

 LINE       2531
 EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T47,T107,T108
1	1	1	Covered	T6,T31,T32

 LINE       2532
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T5,T36,T47
1	1	1	Covered	T6,T31,T32

 LINE       2535
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T31,T32
1	1	0	Covered	T5,T36,T49
1	1	1	Covered	T1,T2,T4

 LINE       2537
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T31
1	1	1	Covered	T6,T31,T32

 LINE       2538
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T36,T84,T85
1	1	1	Covered	T6,T31,T32

 LINE       2541
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T31,T32
1	1	0	Covered	T31,T36,T47
1	1	1	Covered	T1,T2,T4

 LINE       2543
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T107,T109
1	1	1	Covered	T6,T31,T32

 LINE       2544
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T6,T36,T82
1	1	1	Covered	T6,T31,T33

 LINE       2547
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T31,T32
1	1	0	Covered	T5,T36,T49
1	1	1	Covered	T1,T2,T4

 LINE       2549
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T31,T107,T110
1	1	1	Covered	T6,T31,T32

 LINE       2550
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T6,T36,T49
1	1	1	Covered	T6,T31,T32

 LINE       2553
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T49,T82,T84
1	1	1	Covered	T6,T31,T37

 LINE       2736
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T74
1	0	Covered	T32,T33,T74
1	1	Covered	T5,T6,T7

 LINE       2766
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T7,T31,T33
1	0	Covered	T6,T31,T32

---

Branch Coverage for Module : clkmgr_reg_top

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	2452	2	2	100.00
IF	85	3	3	100.00
CASE	2607	23	23	100.00
IF	2720	2	2	100.00
IF	2728	2	2	100.00
CASE	2769	11	11	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv' or '../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2452	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T31
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	85	if ((!rst_ni))
-2-:	87	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T7
0	1	Covered	T6,T31,T47
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	2607	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T5,T6,T31
addr_hit[1]	Covered	T5,T6,T31
addr_hit[2]	Covered	T5,T6,T31
addr_hit[3]	Covered	T5,T6,T31
addr_hit[4]	Covered	T5,T6,T31
addr_hit[5]	Covered	T5,T6,T31
addr_hit[6]	Covered	T5,T6,T31
addr_hit[7]	Covered	T5,T6,T31
addr_hit[8]	Covered	T5,T6,T31
addr_hit[9]	Covered	T5,T6,T31
addr_hit[10]	Covered	T5,T6,T31
addr_hit[11]	Covered	T5,T6,T31
addr_hit[12]	Covered	T5,T6,T31
addr_hit[13]	Covered	T5,T6,T31
addr_hit[14]	Covered	T5,T6,T31
addr_hit[15]	Covered	T5,T6,T31
addr_hit[16]	Covered	T5,T6,T31
addr_hit[17]	Covered	T5,T6,T31
addr_hit[18]	Covered	T5,T6,T31
addr_hit[19]	Covered	T5,T6,T31
addr_hit[20]	Covered	T5,T6,T31
addr_hit[21]	Covered	T5,T6,T31
default	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	2720	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	2728	if ((!rst_shadowed_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	2769	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[10]	Covered	T5,T6,T31
addr_hit[11]	Covered	T5,T6,T31
addr_hit[12]	Covered	T5,T6,T31
addr_hit[13]	Covered	T5,T6,T31
addr_hit[14]	Covered	T5,T6,T31
addr_hit[15]	Covered	T5,T6,T31
addr_hit[16]	Covered	T5,T6,T31
addr_hit[17]	Covered	T5,T6,T31
addr_hit[18]	Covered	T5,T6,T31
addr_hit[19]	Covered	T5,T6,T31
default	Covered	T5,T6,T31

---

Assert Coverage for Module : clkmgr_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	165022201	840341	0	0
reAfterRv	165022201	840340	0	0
rePulse	165022201	196282	0	0
wePulse	165022201	644058	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	165022201	840341	0	0
T5	2291	15	0	0
T6	6075	1019	0	0
T7	822	0	0	0
T31	8934	1018	0	0
T32	6674	270	0	0
T33	5820	304	0	0
T34	1454	0	0	0
T35	2691	256	0	0
T36	7526	42	0	0
T37	1040	86	0	0
T74	0	494	0	0
T75	0	200	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	165022201	840340	0	0
T5	2291	15	0	0
T6	6075	1019	0	0
T7	822	0	0	0
T31	8934	1018	0	0
T32	6674	270	0	0
T33	5820	304	0	0
T34	1454	0	0	0
T35	2691	256	0	0
T36	7526	42	0	0
T37	1040	86	0	0
T74	0	494	0	0
T75	0	200	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	165022201	196282	0	0
T5	2291	2	0	0
T6	6075	590	0	0
T7	822	0	0	0
T31	8934	593	0	0
T32	6674	241	0	0
T33	5820	270	0	0
T34	1454	0	0	0
T35	2691	128	0	0
T36	7526	3	0	0
T37	1040	44	0	0
T74	0	427	0	0
T75	0	163	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	165022201	644058	0	0
T5	2291	13	0	0
T6	6075	429	0	0
T7	822	0	0	0
T31	8934	425	0	0
T32	6674	29	0	0
T33	5820	34	0	0
T34	1454	0	0	0
T35	2691	128	0	0
T36	7526	39	0	0
T37	1040	42	0	0
T74	0	67	0	0
T75	0	37	0	0

Line Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
TOTAL		244	244	100.00
ALWAYS	85	4	4	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
ALWAYS	280	4	4	100.00
CONT_ASSIGN	310	1	1	100.00
ALWAYS	323	3	3	100.00
CONT_ASSIGN	352	1	1	100.00
ALWAYS	366	4	4	100.00
CONT_ASSIGN	396	1	1	100.00
ALWAYS	409	3	3	100.00
CONT_ASSIGN	438	1	1	100.00
ALWAYS	452	4	4	100.00
CONT_ASSIGN	482	1	1	100.00
ALWAYS	495	3	3	100.00
CONT_ASSIGN	524	1	1	100.00
ALWAYS	538	4	4	100.00
CONT_ASSIGN	568	1	1	100.00
ALWAYS	581	3	3	100.00
CONT_ASSIGN	610	1	1	100.00
ALWAYS	624	4	4	100.00
CONT_ASSIGN	654	1	1	100.00
ALWAYS	667	3	3	100.00
CONT_ASSIGN	696	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	768	1	1	100.00
CONT_ASSIGN	1256	1	1	100.00
CONT_ASSIGN	1259	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1413	1	1	100.00
CONT_ASSIGN	1416	1	1	100.00
CONT_ASSIGN	1448	1	1	100.00
CONT_ASSIGN	1571	1	1	100.00
CONT_ASSIGN	1574	1	1	100.00
CONT_ASSIGN	1606	1	1	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1732	1	1	100.00
CONT_ASSIGN	1764	1	1	100.00
CONT_ASSIGN	1887	1	1	100.00
CONT_ASSIGN	1890	1	1	100.00
CONT_ASSIGN	1921	1	1	100.00
ALWAYS	2427	23	23	100.00
CONT_ASSIGN	2452	1	1	100.00
ALWAYS	2456	1	1	100.00
CONT_ASSIGN	2482	1	1	100.00
CONT_ASSIGN	2484	1	1	100.00
CONT_ASSIGN	2486	1	1	100.00
CONT_ASSIGN	2487	1	1	100.00
CONT_ASSIGN	2489	1	1	100.00
CONT_ASSIGN	2490	1	1	100.00
CONT_ASSIGN	2492	1	1	100.00
CONT_ASSIGN	2494	1	1	100.00
CONT_ASSIGN	2495	1	1	100.00
CONT_ASSIGN	2496	1	1	100.00
CONT_ASSIGN	2498	1	1	100.00
CONT_ASSIGN	2499	1	1	100.00
CONT_ASSIGN	2501	1	1	100.00
CONT_ASSIGN	2502	1	1	100.00
CONT_ASSIGN	2504	1	1	100.00
CONT_ASSIGN	2506	1	1	100.00
CONT_ASSIGN	2508	1	1	100.00
CONT_ASSIGN	2510	1	1	100.00
CONT_ASSIGN	2511	1	1	100.00
CONT_ASSIGN	2513	1	1	100.00
CONT_ASSIGN	2515	1	1	100.00
CONT_ASSIGN	2517	1	1	100.00
CONT_ASSIGN	2519	1	1	100.00
CONT_ASSIGN	2520	1	1	100.00
CONT_ASSIGN	2522	1	1	100.00
CONT_ASSIGN	2523	1	1	100.00
CONT_ASSIGN	2525	1	1	100.00
CONT_ASSIGN	2526	1	1	100.00
CONT_ASSIGN	2529	1	1	100.00
CONT_ASSIGN	2531	1	1	100.00
CONT_ASSIGN	2532	1	1	100.00
CONT_ASSIGN	2535	1	1	100.00
CONT_ASSIGN	2537	1	1	100.00
CONT_ASSIGN	2538	1	1	100.00
CONT_ASSIGN	2541	1	1	100.00
CONT_ASSIGN	2543	1	1	100.00
CONT_ASSIGN	2544	1	1	100.00
CONT_ASSIGN	2547	1	1	100.00
CONT_ASSIGN	2549	1	1	100.00
CONT_ASSIGN	2550	1	1	100.00
CONT_ASSIGN	2553	1	1	100.00
CONT_ASSIGN	2555	1	1	100.00
CONT_ASSIGN	2557	1	1	100.00
CONT_ASSIGN	2559	1	1	100.00
CONT_ASSIGN	2561	1	1	100.00
CONT_ASSIGN	2563	1	1	100.00
CONT_ASSIGN	2565	1	1	100.00
CONT_ASSIGN	2567	1	1	100.00
CONT_ASSIGN	2569	1	1	100.00
CONT_ASSIGN	2571	1	1	100.00
CONT_ASSIGN	2573	1	1	100.00
CONT_ASSIGN	2575	1	1	100.00
ALWAYS	2579	23	23	100.00
ALWAYS	2606	47	47	100.00
ALWAYS	2720	3	3	100.00
ALWAYS	2728	3	3	100.00
CONT_ASSIGN	2736	1	1	100.00
CONT_ASSIGN	2739	1	1	100.00
CONT_ASSIGN	2751	1	1	100.00
CONT_ASSIGN	2766	1	1	100.00
ALWAYS	2768	12	12	100.00
CONT_ASSIGN	2813	1	1	100.00
CONT_ASSIGN	2814	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv' or '../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
86	1	1
87	1	1
88	1	1
			MISSING_ELSE
94	1	1
106	1	1
107	1	1
135	1	1
136	1	1
280	1	1
281	1	1
282	1	1
283	1	1
310	1	1
323	1	1
324	1	1
325	1	1
352	1	1
366	1	1
367	1	1
368	1	1
369	1	1
396	1	1
409	1	1
410	1	1
411	1	1
438	1	1
452	1	1
453	1	1
454	1	1
455	1	1
482	1	1
495	1	1
496	1	1
497	1	1
524	1	1
538	1	1
539	1	1
540	1	1
541	1	1
568	1	1
581	1	1
582	1	1
583	1	1
610	1	1
624	1	1
625	1	1
626	1	1
627	1	1
654	1	1
667	1	1
668	1	1
669	1	1
696	1	1
703	1	1
718	1	1
734	1	1
768	1	1
1256	1	1
1259	1	1
1290	1	1
1413	1	1
1416	1	1
1448	1	1
1571	1	1
1574	1	1
1606	1	1
1729	1	1
1732	1	1
1764	1	1
1887	1	1
1890	1	1
1921	1	1
2427	1	1
2428	1	1
2429	1	1
2430	1	1
2431	1	1
2432	1	1
2433	1	1
2434	1	1
2435	1	1
2436	1	1
2437	1	1
2438	1	1
2439	1	1
2440	1	1
2441	1	1
2442	1	1
2443	1	1
2444	1	1
2445	1	1
2446	1	1
2447	1	1
2448	1	1
2449	1	1
2452	1	1
2456	1	1
2482	1	1
2484	1	1
2486	1	1
2487	1	1
2489	1	1
2490	1	1
2492	1	1
2494	1	1
2495	1	1
2496	1	1
2498	1	1
2499	1	1
2501	1	1
2502	1	1
2504	1	1
2506	1	1
2508	1	1
2510	1	1
2511	1	1
2513	1	1
2515	1	1
2517	1	1
2519	1	1
2520	1	1
2522	1	1
2523	1	1
2525	1	1
2526	1	1
2529	1	1
2531	1	1
2532	1	1
2535	1	1
2537	1	1
2538	1	1
2541	1	1
2543	1	1
2544	1	1
2547	1	1
2549	1	1
2550	1	1
2553	1	1
2555	1	1
2557	1	1
2559	1	1
2561	1	1
2563	1	1
2565	1	1
2567	1	1
2569	1	1
2571	1	1
2573	1	1
2575	1	1
2579	1	1
2580	1	1
2581	1	1
2582	1	1
2583	1	1
2584	1	1
2585	1	1
2586	1	1
2587	1	1
2588	1	1
2589	1	1
2590	1	1
2591	1	1
2592	1	1
2593	1	1
2594	1	1
2595	1	1
2596	1	1
2597	1	1
2598	1	1
2599	1	1
2600	1	1
2601	1	1
2606	1	1
2607	1	1
2609	1	1
2610	1	1
2614	1	1
2618	1	1
2619	1	1
2623	1	1
2627	1	1
2631	1	1
2635	1	1
2636	1	1
2637	1	1
2638	1	1
2642	1	1
2643	1	1
2644	1	1
2645	1	1
2649	1	1
2650	1	1
2651	1	1
2652	1	1
2656	1	1
2660	1	1
2663	1	1
2666	1	1
2669	1	1
2672	1	1
2675	1	1
2678	1	1
2681	1	1
2684	1	1
2687	1	1
2690	1	1
2691	1	1
2692	1	1
2693	1	1
2694	1	1
2695	1	1
2696	1	1
2697	1	1
2698	1	1
2699	1	1
2700	1	1
2704	1	1
2705	1	1
2706	1	1
2720	1	1
2721	1	1
2723	1	1
2728	1	1
2729	1	1
2731	1	1
2736	1	1
2739	1	1
2751	1	1
2766	1	1
2768	1	1
2769	1	1
2771	1	1
2774	1	1
2777	1	1
2780	1	1
2783	1	1
2786	1	1
2789	1	1
2792	1	1
2795	1	1
2798	1	1
2813	1	1
2814	1	1

---

Cond Coverage for Instance : tb.dut.u_reg

	Total	Covered	Percent
Conditions	291	291	100.00
Logical	291	291	100.00
Non-Logical	0	0
Event	0	0

 LINE       75
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       87
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T56,T57,T66
1	0	Covered	T6,T31,T47

 LINE       94
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T5,T6,T7
0	0	1	Covered	T56,T57,T66
0	1	0	Covered	T6,T31,T47
1	0	0	Covered	T6,T31,T47

 LINE       136
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T5,T6,T7
0	0	1	Covered	T6,T31,T47
0	1	0	Covered	T5,T36,T81
1	0	0	Covered	T5,T36,T81

 LINE       136
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T31

 LINE       768
 EXPRESSION (extclk_ctrl_we & extclk_ctrl_regwen_qs)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T30,T102,T103
1	1	Covered	T2,T19,T20

 LINE       1259
 EXPRESSION (io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T30,T102,T103
1	1	Covered	T1,T2,T4

 LINE       1290
 EXPRESSION (io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen)
             -------------1-------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T31,T32
1	0	Covered	T6,T31,T35
1	1	Covered	T6,T31,T32

 LINE       1416
 EXPRESSION (io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T30,T102,T103
1	1	Covered	T1,T2,T4

 LINE       1448
 EXPRESSION (io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T31,T32
1	0	Covered	T6,T31,T35
1	1	Covered	T6,T31,T32

 LINE       1574
 EXPRESSION (io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T30,T102,T103
1	1	Covered	T1,T2,T4

 LINE       1606
 EXPRESSION (io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T31,T32
1	0	Covered	T6,T31,T35
1	1	Covered	T6,T31,T32

 LINE       1732
 EXPRESSION (main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T30,T102,T103
1	1	Covered	T1,T2,T4

 LINE       1764
 EXPRESSION (main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen)
             ---------------1---------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T31,T32
1	0	Covered	T6,T31,T47
1	1	Covered	T6,T31,T33

 LINE       1890
 EXPRESSION (usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen)
             -----------1-----------   -------------2-------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T30,T102,T103
1	1	Covered	T1,T2,T4

 LINE       1921
 EXPRESSION (usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T31,T32
1	0	Covered	T6,T31,T35
1	1	Covered	T6,T31,T32

 LINE       2428
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2429
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2430
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T31,T32

 LINE       2431
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_STATUS_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2432
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_REGWEN_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2433
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_ENABLE_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2434
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_ENABLES_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2435
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2436
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_STATUS_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2437
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MEASURE_CTRL_REGWEN_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2438
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_EN_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T31,T32

 LINE       2439
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2440
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T31,T32

 LINE       2441
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2442
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T31,T32

 LINE       2443
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2444
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2445
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2446
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_EN_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T31,T32

 LINE       2447
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2448
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_RECOV_ERR_CODE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2449
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_FATAL_ERR_CODE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T31
1	Covered	T5,T6,T31

 LINE       2452
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T31

 LINE       2452
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31

 LINE       2456
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T5,T6,T31
22 (addr_hit[21] & ((|(4'...	Covered	T5,T6,T31
21 (addr_hit[20] & ((|(4'...	Covered	T5,T6,T31
20 (addr_hit[19] & ((|(4'...	Covered	T5,T6,T31
19 (addr_hit[18] & ((|(4'...	Covered	T5,T31,T32
18 (addr_hit[17] & ((|(4'...	Covered	T5,T6,T31
17 (addr_hit[16] & ((|(4'...	Covered	T5,T6,T31
16 (addr_hit[15] & ((|(4'...	Covered	T5,T6,T31
15 (addr_hit[14] & ((|(4'...	Covered	T5,T31,T32
14 (addr_hit[13] & ((|(4'...	Covered	T5,T6,T31
13 (addr_hit[12] & ((|(4'...	Covered	T5,T31,T32
12 (addr_hit[11] & ((|(4'...	Covered	T5,T6,T31
11 (addr_hit[10] & ((|(4'...	Covered	T5,T31,T32
10 (addr_hit[9] & ((|(4'b...	Covered	T5,T6,T31
9 (addr_hit[8] & ((|(4'b...	Covered	T5,T6,T31
8 (addr_hit[7] & ((|(4'b...	Covered	T5,T6,T31
7 (addr_hit[6] & ((|(4'b...	Covered	T5,T6,T31
6 (addr_hit[5] & ((|(4'b...	Covered	T5,T6,T31
5 (addr_hit[4] & ((|(4'b...	Covered	T5,T6,T31
4 (addr_hit[3] & ((|(4'b...	Covered	T5,T6,T31
3 (addr_hit[2] & ((|(4'b...	Covered	T5,T31,T32
2 (addr_hit[1] & ((|(4'b...	Covered	T5,T6,T31
1 (addr_hit[0] & ((|(4'b...	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T31,T32
1	1	Covered	T5,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T31,T32
1	1	Covered	T5,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T31,T32
1	1	Covered	T5,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T31,T32
1	1	Covered	T5,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T31,T32
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T31,T32
1	1	Covered	T5,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T6,T31
1	1	Covered	T5,T6,T31

 LINE       2482
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T31,T36,T49
1	1	1	Covered	T6,T31,T35

 LINE       2487
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T5,T31,T36
1	1	1	Covered	T6,T31,T35

 LINE       2490
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T31,T32
1	1	0	Covered	T5,T36,T82
1	1	1	Covered	T2,T19,T20

 LINE       2495
 EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T83,T104,T105
1	1	1	Covered	T6,T31,T32

 LINE       2496
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T36,T84,T86
1	1	1	Covered	T6,T31,T35

 LINE       2499
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T5,T6,T36
1	1	1	Covered	T6,T31,T35

 LINE       2502
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T5,T36,T49
1	1	1	Covered	T6,T31,T35

 LINE       2511
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T5,T6,T36
1	1	1	Covered	T6,T31,T35

 LINE       2520
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T36,T81,T82
1	1	1	Covered	T6,T31,T35

 LINE       2523
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T31,T32
1	1	0	Covered	T36,T47,T49
1	1	1	Covered	T1,T2,T4

 LINE       2525
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T6,T106
1	1	1	Covered	T6,T31,T32

 LINE       2526
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T5,T36,T47
1	1	1	Covered	T6,T31,T32

 LINE       2529
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T31,T32
1	1	0	Covered	T49,T82,T84
1	1	1	Covered	T1,T2,T4

 LINE       2531
 EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T47,T107,T108
1	1	1	Covered	T6,T31,T32

 LINE       2532
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T5,T36,T47
1	1	1	Covered	T6,T31,T32

 LINE       2535
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T31,T32
1	1	0	Covered	T5,T36,T49
1	1	1	Covered	T1,T2,T4

 LINE       2537
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T31
1	1	1	Covered	T6,T31,T32

 LINE       2538
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T36,T84,T85
1	1	1	Covered	T6,T31,T32

 LINE       2541
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T31,T32
1	1	0	Covered	T31,T36,T47
1	1	1	Covered	T1,T2,T4

 LINE       2543
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T107,T109
1	1	1	Covered	T6,T31,T32

 LINE       2544
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T6,T36,T82
1	1	1	Covered	T6,T31,T33

 LINE       2547
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T31,T32
1	1	0	Covered	T5,T36,T49
1	1	1	Covered	T1,T2,T4

 LINE       2549
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T31,T107,T110
1	1	1	Covered	T6,T31,T32

 LINE       2550
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T6,T36,T49
1	1	1	Covered	T6,T31,T32

 LINE       2553
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T31,T32
1	0	1	Covered	T5,T6,T31
1	1	0	Covered	T49,T82,T84
1	1	1	Covered	T6,T31,T37

 LINE       2736
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T74
1	0	Covered	T32,T33,T74
1	1	Covered	T5,T6,T7

 LINE       2766
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T7,T31,T33
1	0	Covered	T6,T31,T32

---

Branch Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	2452	2	2	100.00
IF	85	3	3	100.00
CASE	2607	23	23	100.00
IF	2720	2	2	100.00
IF	2728	2	2	100.00
CASE	2769	11	11	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv' or '../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2452	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T31
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	85	if ((!rst_ni))
-2-:	87	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T7
0	1	Covered	T6,T31,T47
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	2607	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T5,T6,T31
addr_hit[1]	Covered	T5,T6,T31
addr_hit[2]	Covered	T5,T6,T31
addr_hit[3]	Covered	T5,T6,T31
addr_hit[4]	Covered	T5,T6,T31
addr_hit[5]	Covered	T5,T6,T31
addr_hit[6]	Covered	T5,T6,T31
addr_hit[7]	Covered	T5,T6,T31
addr_hit[8]	Covered	T5,T6,T31
addr_hit[9]	Covered	T5,T6,T31
addr_hit[10]	Covered	T5,T6,T31
addr_hit[11]	Covered	T5,T6,T31
addr_hit[12]	Covered	T5,T6,T31
addr_hit[13]	Covered	T5,T6,T31
addr_hit[14]	Covered	T5,T6,T31
addr_hit[15]	Covered	T5,T6,T31
addr_hit[16]	Covered	T5,T6,T31
addr_hit[17]	Covered	T5,T6,T31
addr_hit[18]	Covered	T5,T6,T31
addr_hit[19]	Covered	T5,T6,T31
addr_hit[20]	Covered	T5,T6,T31
addr_hit[21]	Covered	T5,T6,T31
default	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	2720	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	2728	if ((!rst_shadowed_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	2769	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[10]	Covered	T5,T6,T31
addr_hit[11]	Covered	T5,T6,T31
addr_hit[12]	Covered	T5,T6,T31
addr_hit[13]	Covered	T5,T6,T31
addr_hit[14]	Covered	T5,T6,T31
addr_hit[15]	Covered	T5,T6,T31
addr_hit[16]	Covered	T5,T6,T31
addr_hit[17]	Covered	T5,T6,T31
addr_hit[18]	Covered	T5,T6,T31
addr_hit[19]	Covered	T5,T6,T31
default	Covered	T5,T6,T31

---

Assert Coverage for Instance : tb.dut.u_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	165022201	840341	0	0
reAfterRv	165022201	840340	0	0
rePulse	165022201	196282	0	0
wePulse	165022201	644058	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	165022201	840341	0	0
T5	2291	15	0	0
T6	6075	1019	0	0
T7	822	0	0	0
T31	8934	1018	0	0
T32	6674	270	0	0
T33	5820	304	0	0
T34	1454	0	0	0
T35	2691	256	0	0
T36	7526	42	0	0
T37	1040	86	0	0
T74	0	494	0	0
T75	0	200	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	165022201	840340	0	0
T5	2291	15	0	0
T6	6075	1019	0	0
T7	822	0	0	0
T31	8934	1018	0	0
T32	6674	270	0	0
T33	5820	304	0	0
T34	1454	0	0	0
T35	2691	256	0	0
T36	7526	42	0	0
T37	1040	86	0	0
T74	0	494	0	0
T75	0	200	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	165022201	196282	0	0
T5	2291	2	0	0
T6	6075	590	0	0
T7	822	0	0	0
T31	8934	593	0	0
T32	6674	241	0	0
T33	5820	270	0	0
T34	1454	0	0	0
T35	2691	128	0	0
T36	7526	3	0	0
T37	1040	44	0	0
T74	0	427	0	0
T75	0	163	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	165022201	644058	0	0
T5	2291	13	0	0
T6	6075	429	0	0
T7	822	0	0	0
T31	8934	425	0	0
T32	6674	29	0	0
T33	5820	34	0	0
T34	1454	0	0	0
T35	2691	128	0	0
T36	7526	39	0	0
T37	1040	42	0	0
T74	0	67	0	0
T75	0	37	0	0