Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Unreachable
1	0	Covered	T1,T2,T56

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	164108189	161356997	0	0
AllClkBypReqTrue_A	164108189	130284	0	0
IoClkBypReqFalse_A	164108189	161272837	0	2397
IoClkBypReqTrue_A	164108189	209912	0	0
LcClkBypAckFalse_A	164108189	161364274	0	0
LcClkBypAckTrue_A	164108189	123007	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164108189	161356997	0	0
T1	72793	72728	0	0
T2	433808	433083	0	0
T4	225024	224941	0	0
T18	1194	1014	0	0
T19	1934	1684	0	0
T20	1857	1629	0	0
T21	1477	1251	0	0
T22	1818	1793	0	0
T23	1831	1657	0	0
T24	1942	1842	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164108189	130284	0	0
T2	433808	2441	0	0
T4	225024	0	0	0
T11	0	232	0	0
T12	0	374	0	0
T18	1194	0	0	0
T19	1934	88	0	0
T20	1857	193	0	0
T21	1477	99	0	0
T22	1818	0	0	0
T23	1831	0	0	0
T24	1942	0	0	0
T28	209105	0	0	0
T69	0	20	0	0
T73	0	167	0	0
T111	0	318	0	0
T112	0	53	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164108189	161272837	0	2397
T1	72793	72724	0	3
T2	433808	432935	0	3
T4	225024	224939	0	3
T18	1194	1012	0	3
T19	1934	1701	0	3
T20	1857	1462	0	3
T21	1477	1348	0	3
T22	1818	1791	0	3
T23	1831	1521	0	3
T24	1942	1840	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164108189	209912	0	0
T2	433808	3897	0	0
T4	225024	0	0	0
T11	0	556	0	0
T12	0	567	0	0
T18	1194	0	0	0
T19	1934	69	0	0
T20	1857	358	0	0
T21	1477	0	0	0
T22	1818	0	0	0
T23	1831	134	0	0
T24	1942	0	0	0
T28	209105	0	0	0
T69	0	47	0	0
T73	0	90	0	0
T111	0	581	0	0
T113	0	141	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164108189	161364274	0	0
T1	72793	72728	0	0
T2	433808	433103	0	0
T4	225024	224941	0	0
T18	1194	1014	0	0
T19	1934	1710	0	0
T20	1857	1712	0	0
T21	1477	1350	0	0
T22	1818	1793	0	0
T23	1831	1612	0	0
T24	1942	1842	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164108189	123007	0	0
T2	433808	2236	0	0
T4	225024	0	0	0
T11	0	357	0	0
T12	0	311	0	0
T18	1194	0	0	0
T19	1934	62	0	0
T20	1857	110	0	0
T21	1477	0	0	0
T22	1818	0	0	0
T23	1831	45	0	0
T24	1942	0	0	0
T28	209105	0	0	0
T69	0	5	0	0
T73	0	44	0	0
T111	0	424	0	0
T113	0	117	0	0