Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1693609516	15855	0	0
TransStop_A	1693609516	8238	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1693609516	15855	0	0
T1	1189244	9	0	0
T2	715580	671	0	0
T4	870456	0	0	0
T11	0	128	0	0
T18	4872	0	0	0
T19	8140	0	0	0
T20	29736	0	0	0
T21	9236	0	0	0
T22	33076	16	0	0
T23	7792	0	0	0
T24	16536	21	0	0
T68	0	4	0	0
T70	0	28	0	0
T114	0	16	0	0
T115	0	4	0	0
T116	0	19	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1693609516	8238	0	0
T1	1189244	7	0	0
T2	715580	326	0	0
T4	870456	0	0	0
T11	0	58	0	0
T18	4872	0	0	0
T19	8140	0	0	0
T20	29736	0	0	0
T21	9236	0	0	0
T22	33076	12	0	0
T23	7792	0	0	0
T24	16536	13	0	0
T68	0	4	0	0
T70	0	10	0	0
T114	0	10	0	0
T115	0	4	0	0
T116	0	11	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	423402379	3971	0	0
TransStop_A	423402379	2071	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423402379	3971	0	0
T1	297311	3	0	0
T2	178895	160	0	0
T4	217614	0	0	0
T11	0	30	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7434	0	0	0
T21	2309	0	0	0
T22	8269	3	0	0
T23	1948	0	0	0
T24	4134	4	0	0
T68	0	1	0	0
T70	0	7	0	0
T114	0	5	0	0
T115	0	1	0	0
T116	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423402379	2071	0	0
T1	297311	2	0	0
T2	178895	77	0	0
T4	217614	0	0	0
T11	0	11	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7434	0	0	0
T21	2309	0	0	0
T22	8269	2	0	0
T23	1948	0	0	0
T24	4134	3	0	0
T68	0	1	0	0
T70	0	3	0	0
T114	0	3	0	0
T115	0	1	0	0
T116	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	423402379	3979	0	0
TransStop_A	423402379	2044	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423402379	3979	0	0
T1	297311	3	0	0
T2	178895	180	0	0
T4	217614	0	0	0
T11	0	34	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7434	0	0	0
T21	2309	0	0	0
T22	8269	3	0	0
T23	1948	0	0	0
T24	4134	4	0	0
T68	0	1	0	0
T70	0	8	0	0
T114	0	4	0	0
T115	0	1	0	0
T116	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423402379	2044	0	0
T1	297311	2	0	0
T2	178895	88	0	0
T4	217614	0	0	0
T11	0	14	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7434	0	0	0
T21	2309	0	0	0
T22	8269	2	0	0
T23	1948	0	0	0
T24	4134	3	0	0
T68	0	1	0	0
T70	0	3	0	0
T114	0	3	0	0
T115	0	1	0	0
T116	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	423402379	3943	0	0
TransStop_A	423402379	2041	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423402379	3943	0	0
T1	297311	1	0	0
T2	178895	165	0	0
T4	217614	0	0	0
T11	0	31	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7434	0	0	0
T21	2309	0	0	0
T22	8269	5	0	0
T23	1948	0	0	0
T24	4134	8	0	0
T68	0	1	0	0
T70	0	7	0	0
T114	0	2	0	0
T115	0	1	0	0
T116	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423402379	2041	0	0
T1	297311	1	0	0
T2	178895	84	0	0
T4	217614	0	0	0
T11	0	15	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7434	0	0	0
T21	2309	0	0	0
T22	8269	5	0	0
T23	1948	0	0	0
T24	4134	4	0	0
T68	0	1	0	0
T70	0	2	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	423402379	3962	0	0
TransStop_A	423402379	2082	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423402379	3962	0	0
T1	297311	2	0	0
T2	178895	166	0	0
T4	217614	0	0	0
T11	0	33	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7434	0	0	0
T21	2309	0	0	0
T22	8269	5	0	0
T23	1948	0	0	0
T24	4134	5	0	0
T68	0	1	0	0
T70	0	6	0	0
T114	0	5	0	0
T115	0	1	0	0
T116	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423402379	2082	0	0
T1	297311	2	0	0
T2	178895	77	0	0
T4	217614	0	0	0
T11	0	18	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7434	0	0	0
T21	2309	0	0	0
T22	8269	3	0	0
T23	1948	0	0	0
T24	4134	3	0	0
T68	0	1	0	0
T70	0	2	0	0
T114	0	3	0	0
T115	0	1	0	0
T116	0	2	0	0