Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T18
01CoveredT1,T2,T18
10CoveredT2,T19,T20 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T18
10CoveredT2,T19,T20
11CoveredT2,T19,T20 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T19,T20
10CoveredT1,T2,T18
11CoveredT1,T2,T18
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 493400510 493398113 0 0
selKnown1 1189644981 1189642584 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 493400510 493398113 0 0
T1 349341 349338 0 0
T2 2116810 2116810 0 0
T4 196300 196297 0 0
T18 1397 1394 0 0
T19 2348 2345 0 0
T20 9318 9315 0 0
T21 2709 2706 0 0
T22 9893 9890 0 0
T23 2326 2323 0 0
T24 4810 4807 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1189644981 1189642584 0 0
T1 838944 838941 0 0
T2 508116 508116 0 0
T4 471195 471192 0 0
T18 3507 3504 0 0
T19 5859 5856 0 0
T20 21405 21402 0 0
T21 6648 6645 0 0
T22 23817 23814 0 0
T23 5607 5604 0 0
T24 11907 11904 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T18
01CoveredT1,T2,T18
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T18
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T18
11CoveredT1,T2,T18
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 197459271 197458472 0 0
selKnown1 396548327 396547528 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 197459271 197458472 0 0
T1 139736 139735 0 0
T2 846979 846979 0 0
T4 78520 78519 0 0
T18 559 558 0 0
T19 955 954 0 0
T20 3865 3864 0 0
T21 1099 1098 0 0
T22 3957 3956 0 0
T23 940 939 0 0
T24 1924 1923 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 396548327 396547528 0 0
T1 279648 279647 0 0
T2 169372 169372 0 0
T4 157065 157064 0 0
T18 1169 1168 0 0
T19 1953 1952 0 0
T20 7135 7134 0 0
T21 2216 2215 0 0
T22 7939 7938 0 0
T23 1869 1868 0 0
T24 3969 3968 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T18
01CoveredT1,T2,T18
10CoveredT2,T19,T20 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T18
10CoveredT2,T19,T20
11CoveredT2,T19,T20 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T19,T20
10CoveredT1,T2,T18
11CoveredT1,T2,T18
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 197212196 197211397 0 0
selKnown1 396548327 396547528 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 197212196 197211397 0 0
T1 139736 139735 0 0
T2 846343 846343 0 0
T4 78520 78519 0 0
T18 559 558 0 0
T19 916 915 0 0
T20 3521 3520 0 0
T21 1062 1061 0 0
T22 3957 3956 0 0
T23 916 915 0 0
T24 1924 1923 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 396548327 396547528 0 0
T1 279648 279647 0 0
T2 169372 169372 0 0
T4 157065 157064 0 0
T18 1169 1168 0 0
T19 1953 1952 0 0
T20 7135 7134 0 0
T21 2216 2215 0 0
T22 7939 7938 0 0
T23 1869 1868 0 0
T24 3969 3968 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T18
01CoveredT1,T2,T18
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T18
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T18
11CoveredT1,T2,T18
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 98729043 98728244 0 0
selKnown1 396548327 396547528 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 98729043 98728244 0 0
T1 69869 69868 0 0
T2 423488 423488 0 0
T4 39260 39259 0 0
T18 279 278 0 0
T19 477 476 0 0
T20 1932 1931 0 0
T21 548 547 0 0
T22 1979 1978 0 0
T23 470 469 0 0
T24 962 961 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 396548327 396547528 0 0
T1 279648 279647 0 0
T2 169372 169372 0 0
T4 157065 157064 0 0
T18 1169 1168 0 0
T19 1953 1952 0 0
T20 7135 7134 0 0
T21 2216 2215 0 0
T22 7939 7938 0 0
T23 1869 1868 0 0
T24 3969 3968 0 0

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