Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	164108189	17175652	0	65

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164108189	17175652	0	65
T1	72793	13253	0	0
T2	433808	88041	0	0
T3	0	3603	0	1
T4	225024	0	0	0
T11	0	20642	0	0
T12	0	8975	0	1
T13	0	25263	0	1
T14	0	12983	0	1
T15	0	12596	0	1
T16	0	322113	0	0
T17	0	24705	0	1
T18	1194	0	0	0
T19	1934	0	0	0
T20	1857	0	0	0
T21	1477	0	0	0
T22	1818	0	0	0
T23	1831	0	0	0
T24	1942	0	0	0
T25	0	0	0	1
T26	0	0	0	1
T117	0	0	0	1
T118	0	0	0	1