Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	165022201	5564107	0	0
clk_enables_rd_A	165022201	31187	0	0
clk_hints_rd_A	165022201	28945	0	0
extclk_ctrl_rd_A	165022201	34381	0	0
extclk_ctrl_regwen_rd_A	165022201	25953	0	0
jitter_enable_rd_A	165022201	40446	0	0
jitter_regwen_rd_A	165022201	28561	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165022201	5564107	0	0
T5	2291	182	0	0
T6	6075	9	0	0
T7	822	0	0	0
T31	8934	5	0	0
T32	6674	0	0	0
T33	5820	0	0	0
T34	1454	0	0	0
T35	2691	0	0	0
T36	7526	363	0	0
T37	1040	0	0	0
T47	0	4	0	0
T48	0	42	0	0
T49	0	169	0	0
T81	0	540	0	0
T91	0	4	0	0
T132	0	31	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165022201	31187	0	0
T31	8934	93	0	0
T32	6674	0	0	0
T33	5820	21	0	0
T34	1454	0	0	0
T35	2691	0	0	0
T36	7526	0	0	0
T37	1040	0	0	0
T47	12499	175	0	0
T50	0	4	0	0
T74	5326	0	0	0
T75	5206	0	0	0
T76	0	426	0	0
T83	0	83	0	0
T88	0	29	0	0
T91	0	82	0	0
T99	0	15	0	0
T100	0	152	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165022201	28945	0	0
T31	8934	115	0	0
T32	6674	0	0	0
T33	5820	6	0	0
T34	1454	0	0	0
T35	2691	0	0	0
T36	7526	0	0	0
T37	1040	0	0	0
T47	12499	111	0	0
T74	5326	0	0	0
T75	5206	0	0	0
T76	0	442	0	0
T83	0	62	0	0
T88	0	18	0	0
T91	0	125	0	0
T99	0	17	0	0
T100	0	156	0	0
T132	0	12	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165022201	34381	0	0
T31	8934	1	0	0
T32	6674	0	0	0
T33	5820	14	0	0
T34	1454	0	0	0
T35	2691	0	0	0
T36	7526	0	0	0
T37	1040	0	0	0
T47	12499	6	0	0
T50	0	14	0	0
T74	5326	0	0	0
T75	5206	0	0	0
T76	0	34	0	0
T95	0	63	0	0
T100	0	152	0	0
T121	0	66	0	0
T133	0	3	0	0
T134	0	25	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165022201	25953	0	0
T31	8934	42	0	0
T32	6674	0	0	0
T33	5820	27	0	0
T34	1454	0	0	0
T35	2691	0	0	0
T36	7526	0	0	0
T37	1040	0	0	0
T47	12499	58	0	0
T74	5326	0	0	0
T75	5206	0	0	0
T76	0	198	0	0
T83	0	38	0	0
T88	0	11	0	0
T91	0	45	0	0
T99	0	7	0	0
T100	0	110	0	0
T132	0	9	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165022201	40446	0	0
T31	8934	66	0	0
T32	6674	0	0	0
T33	5820	22	0	0
T34	1454	0	0	0
T35	2691	0	0	0
T36	7526	0	0	0
T37	1040	0	0	0
T47	12499	73	0	0
T50	0	3	0	0
T74	5326	0	0	0
T75	5206	0	0	0
T76	0	214	0	0
T83	0	34	0	0
T88	0	9	0	0
T91	0	42	0	0
T99	0	6	0	0
T100	0	133	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165022201	28561	0	0
T31	8934	50	0	0
T32	6674	0	0	0
T33	5820	24	0	0
T34	1454	0	0	0
T35	2691	0	0	0
T36	7526	0	0	0
T37	1040	0	0	0
T47	12499	26	0	0
T50	0	7	0	0
T74	5326	0	0	0
T75	5206	0	0	0
T76	0	163	0	0
T83	0	37	0	0
T88	0	11	0	0
T91	0	38	0	0
T99	0	6	0	0
T100	0	126	0	0