Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T2,T20,T21
1	1	Covered	T2,T19,T20

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	396548768	4285	0	0
g_div2.Div2Whole_A	396548768	5266	0	0
g_div4.Div4Stepped_A	197459659	4173	0	0
g_div4.Div4Whole_A	197459659	4896	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396548768	4285	0	0
T2	169372	125	0	0
T4	157065	0	0	0
T11	0	15	0	0
T12	0	10	0	0
T18	1170	0	0	0
T19	1954	2	0	0
T20	7136	5	0	0
T21	2217	3	0	0
T22	7939	0	0	0
T23	1869	1	0	0
T24	3969	0	0	0
T28	157267	0	0	0
T69	0	3	0	0
T73	0	1	0	0
T111	0	14	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396548768	5266	0	0
T2	169372	139	0	0
T4	157065	0	0	0
T11	0	15	0	0
T12	0	10	0	0
T18	1170	0	0	0
T19	1954	3	0	0
T20	7136	6	0	0
T21	2217	3	0	0
T22	7939	0	0	0
T23	1869	2	0	0
T24	3969	0	0	0
T28	157267	0	0	0
T69	0	3	0	0
T73	0	9	0	0
T111	0	14	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197459659	4173	0	0
T2	846979	125	0	0
T4	78521	0	0	0
T11	0	15	0	0
T12	0	10	0	0
T18	559	0	0	0
T19	956	2	0	0
T20	3865	5	0	0
T21	1099	3	0	0
T22	3958	0	0	0
T23	940	1	0	0
T24	1925	0	0	0
T28	78566	0	0	0
T69	0	3	0	0
T73	0	1	0	0
T111	0	14	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197459659	4896	0	0
T2	846979	139	0	0
T4	78521	0	0	0
T11	0	15	0	0
T12	0	10	0	0
T18	559	0	0	0
T19	956	2	0	0
T20	3865	6	0	0
T21	1099	3	0	0
T22	3958	0	0	0
T23	940	1	0	0
T24	1925	0	0	0
T28	78566	0	0	0
T69	0	3	0	0
T73	0	8	0	0
T111	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T2,T20,T21
1	1	Covered	T2,T19,T20

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	396548768	4285	0	0
g_div2.Div2Whole_A	396548768	5266	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396548768	4285	0	0
T2	169372	125	0	0
T4	157065	0	0	0
T11	0	15	0	0
T12	0	10	0	0
T18	1170	0	0	0
T19	1954	2	0	0
T20	7136	5	0	0
T21	2217	3	0	0
T22	7939	0	0	0
T23	1869	1	0	0
T24	3969	0	0	0
T28	157267	0	0	0
T69	0	3	0	0
T73	0	1	0	0
T111	0	14	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396548768	5266	0	0
T2	169372	139	0	0
T4	157065	0	0	0
T11	0	15	0	0
T12	0	10	0	0
T18	1170	0	0	0
T19	1954	3	0	0
T20	7136	6	0	0
T21	2217	3	0	0
T22	7939	0	0	0
T23	1869	2	0	0
T24	3969	0	0	0
T28	157267	0	0	0
T69	0	3	0	0
T73	0	9	0	0
T111	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T2,T20,T21
1	1	Covered	T2,T19,T20

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	197459659	4173	0	0
g_div4.Div4Whole_A	197459659	4896	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197459659	4173	0	0
T2	846979	125	0	0
T4	78521	0	0	0
T11	0	15	0	0
T12	0	10	0	0
T18	559	0	0	0
T19	956	2	0	0
T20	3865	5	0	0
T21	1099	3	0	0
T22	3958	0	0	0
T23	940	1	0	0
T24	1925	0	0	0
T28	78566	0	0	0
T69	0	3	0	0
T73	0	1	0	0
T111	0	14	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197459659	4896	0	0
T2	846979	139	0	0
T4	78521	0	0	0
T11	0	15	0	0
T12	0	10	0	0
T18	559	0	0	0
T19	956	2	0	0
T20	3865	6	0	0
T21	1099	3	0	0
T22	3958	0	0	0
T23	940	1	0	0
T24	1925	0	0	0
T28	78566	0	0	0
T69	0	3	0	0
T73	0	8	0	0
T111	0	14	0	0