Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T56
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T18

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48241	0	0
CgEnOn_A	2147483647	39210	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48241	0	0
T1	1824083	38	0	0
T2	3015281	681	0	0
T4	1246877	3	0	0
T14	732367	0	0	0
T17	283457	0	0	0
T18	7463	10	0	0
T19	12501	3	0	0
T20	46232	3	0	0
T21	14207	3	0	0
T22	50920	6	0	0
T23	12001	3	0	0
T24	25376	7	0	0
T44	38077	25	0	0
T45	8513	10	0	0
T46	0	35	0	0
T68	0	1	0	0
T135	0	5	0	0
T136	0	25	0	0
T137	0	25	0	0
T138	0	15	0	0
T142	18329	0	0	0
T143	8246	0	0	0
T144	8415	0	0	0
T145	7605	0	0	0
T146	1183329	0	0	0
T147	18455	0	0	0
T149	0	15	0	0
T150	0	10	0	0
T151	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39210	0	0
T1	1824083	21	0	0
T2	3015281	324	0	0
T4	1246877	0	0	0
T11	0	92	0	0
T12	0	28	0	0
T14	732367	0	0	0
T17	283457	0	0	0
T18	7463	3	0	0
T19	12501	0	0	0
T20	46232	0	0	0
T21	14207	0	0	0
T22	50920	0	0	0
T23	12001	0	0	0
T24	25376	0	0	0
T44	38077	25	0	0
T45	8513	10	0	0
T46	0	35	0	0
T68	0	2	0	0
T72	0	21	0	0
T115	0	2	0	0
T135	0	5	0	0
T136	0	25	0	0
T137	0	25	0	0
T138	0	15	0	0
T139	0	3	0	0
T142	18329	0	0	0
T143	8246	0	0	0
T144	8415	0	0	0
T145	7605	0	0	0
T146	1183329	0	0	0
T147	18455	0	0	0
T149	0	12	0	0
T150	0	10	0	0
T151	0	8	0	0
T152	0	2	0	0
T153	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T56
1	0	Unreachable
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	197459271	169	0	0
CgEnOn_A	197459271	169	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197459271	169	0	0
T14	84469	0	0	0
T17	32683	0	0	0
T44	4552	5	0	0
T45	982	2	0	0
T46	0	7	0	0
T135	0	1	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	3	0	0
T142	2072	0	0	0
T143	966	0	0	0
T144	1027	0	0	0
T145	838	0	0	0
T146	132301	0	0	0
T147	2234	0	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197459271	169	0	0
T14	84469	0	0	0
T17	32683	0	0	0
T44	4552	5	0	0
T45	982	2	0	0
T46	0	7	0	0
T135	0	1	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	3	0	0
T142	2072	0	0	0
T143	966	0	0	0
T144	1027	0	0	0
T145	838	0	0	0
T146	132301	0	0	0
T147	2234	0	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T56
1	0	Unreachable
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	98729043	169	0	0
CgEnOn_A	98729043	169	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98729043	169	0	0
T14	42235	0	0	0
T17	16341	0	0	0
T44	2276	5	0	0
T45	491	2	0	0
T46	0	7	0	0
T135	0	1	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	3	0	0
T142	1036	0	0	0
T143	483	0	0	0
T144	512	0	0	0
T145	419	0	0	0
T146	66150	0	0	0
T147	1116	0	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98729043	169	0	0
T14	42235	0	0	0
T17	16341	0	0	0
T44	2276	5	0	0
T45	491	2	0	0
T46	0	7	0	0
T135	0	1	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	3	0	0
T142	1036	0	0	0
T143	483	0	0	0
T144	512	0	0	0
T145	419	0	0	0
T146	66150	0	0	0
T147	1116	0	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T56
1	0	Unreachable
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	396548327	169	0	0
CgEnOn_A	396548327	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396548327	169	0	0
T14	169031	0	0	0
T17	65431	0	0	0
T44	9169	5	0	0
T45	1988	2	0	0
T46	0	7	0	0
T135	0	1	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	3	0	0
T142	4265	0	0	0
T143	1891	0	0	0
T144	1898	0	0	0
T145	1786	0	0	0
T146	264830	0	0	0
T147	4175	0	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396548327	161	0	0
T14	169031	0	0	0
T17	65431	0	0	0
T44	9169	5	0	0
T45	1988	2	0	0
T46	0	7	0	0
T135	0	1	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	3	0	0
T139	0	3	0	0
T140	0	5	0	0
T142	4265	0	0	0
T143	1891	0	0	0
T144	1898	0	0	0
T145	1786	0	0	0
T146	264830	0	0	0
T147	4175	0	0	0
T150	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T56
1	0	Unreachable
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	423401940	162	0	0
CgEnOn_A	423401940	162	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423401940	162	0	0
T14	176081	0	0	0
T17	68160	0	0	0
T44	8764	4	0	0
T45	2035	3	0	0
T46	0	6	0	0
T135	0	1	0	0
T136	0	6	0	0
T137	0	4	0	0
T138	0	3	0	0
T139	0	2	0	0
T140	0	5	0	0
T142	4442	0	0	0
T143	1970	0	0	0
T144	1977	0	0	0
T145	1862	0	0	0
T146	293874	0	0	0
T147	4349	0	0	0
T151	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423401940	162	0	0
T14	176081	0	0	0
T17	68160	0	0	0
T44	8764	4	0	0
T45	2035	3	0	0
T46	0	6	0	0
T135	0	1	0	0
T136	0	6	0	0
T137	0	4	0	0
T138	0	3	0	0
T139	0	2	0	0
T140	0	5	0	0
T142	4442	0	0	0
T143	1970	0	0	0
T144	1977	0	0	0
T145	1862	0	0	0
T146	293874	0	0	0
T147	4349	0	0	0
T151	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T56
1	0	Unreachable
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	98729043	169	0	0
CgEnOn_A	98729043	169	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98729043	169	0	0
T14	42235	0	0	0
T17	16341	0	0	0
T44	2276	5	0	0
T45	491	2	0	0
T46	0	7	0	0
T135	0	1	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	3	0	0
T142	1036	0	0	0
T143	483	0	0	0
T144	512	0	0	0
T145	419	0	0	0
T146	66150	0	0	0
T147	1116	0	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98729043	169	0	0
T14	42235	0	0	0
T17	16341	0	0	0
T44	2276	5	0	0
T45	491	2	0	0
T46	0	7	0	0
T135	0	1	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	3	0	0
T142	1036	0	0	0
T143	483	0	0	0
T144	512	0	0	0
T145	419	0	0	0
T146	66150	0	0	0
T147	1116	0	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T56
1	0	Unreachable
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	423401940	162	0	0
CgEnOn_A	423401940	162	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423401940	162	0	0
T14	176081	0	0	0
T17	68160	0	0	0
T44	8764	4	0	0
T45	2035	3	0	0
T46	0	6	0	0
T135	0	1	0	0
T136	0	6	0	0
T137	0	4	0	0
T138	0	3	0	0
T139	0	2	0	0
T140	0	5	0	0
T142	4442	0	0	0
T143	1970	0	0	0
T144	1977	0	0	0
T145	1862	0	0	0
T146	293874	0	0	0
T147	4349	0	0	0
T151	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423401940	162	0	0
T14	176081	0	0	0
T17	68160	0	0	0
T44	8764	4	0	0
T45	2035	3	0	0
T46	0	6	0	0
T135	0	1	0	0
T136	0	6	0	0
T137	0	4	0	0
T138	0	3	0	0
T139	0	2	0	0
T140	0	5	0	0
T142	4442	0	0	0
T143	1970	0	0	0
T144	1977	0	0	0
T145	1862	0	0	0
T146	293874	0	0	0
T147	4349	0	0	0
T151	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T56
1	0	Unreachable
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	98729043	169	0	0
CgEnOn_A	98729043	169	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98729043	169	0	0
T14	42235	0	0	0
T17	16341	0	0	0
T44	2276	5	0	0
T45	491	2	0	0
T46	0	7	0	0
T135	0	1	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	3	0	0
T142	1036	0	0	0
T143	483	0	0	0
T144	512	0	0	0
T145	419	0	0	0
T146	66150	0	0	0
T147	1116	0	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98729043	169	0	0
T14	42235	0	0	0
T17	16341	0	0	0
T44	2276	5	0	0
T45	491	2	0	0
T46	0	7	0	0
T135	0	1	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	3	0	0
T142	1036	0	0	0
T143	483	0	0	0
T144	512	0	0	0
T145	419	0	0	0
T146	66150	0	0	0
T147	1116	0	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	197459271	7734	0	0
CgEnOn_A	197459271	5482	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197459271	7734	0	0
T1	139736	13	0	0
T2	846979	174	0	0
T4	78520	1	0	0
T18	559	3	0	0
T19	955	1	0	0
T20	3865	1	0	0
T21	1099	1	0	0
T22	3957	1	0	0
T23	940	1	0	0
T24	1924	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197459271	5482	0	0
T1	139736	11	0	0
T2	846979	163	0	0
T4	78520	0	0	0
T11	0	46	0	0
T12	0	14	0	0
T18	559	2	0	0
T19	955	0	0	0
T20	3865	0	0	0
T21	1099	0	0	0
T22	3957	0	0	0
T23	940	0	0	0
T24	1924	0	0	0
T68	0	1	0	0
T72	0	11	0	0
T115	0	1	0	0
T152	0	1	0	0
T153	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	98729043	7235	0	0
CgEnOn_A	98729043	4981	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98729043	7235	0	0
T1	69869	12	0	0
T2	423488	172	0	0
T4	39260	1	0	0
T18	279	2	0	0
T19	477	1	0	0
T20	1932	1	0	0
T21	548	1	0	0
T22	1979	1	0	0
T23	470	1	0	0
T24	962	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98729043	4981	0	0
T1	69869	10	0	0
T2	423488	161	0	0
T4	39260	0	0	0
T11	0	46	0	0
T12	0	14	0	0
T18	279	1	0	0
T19	477	0	0	0
T20	1932	0	0	0
T21	548	0	0	0
T22	1979	0	0	0
T23	470	0	0	0
T24	962	0	0	0
T68	0	1	0	0
T72	0	10	0	0
T115	0	1	0	0
T152	0	1	0	0
T153	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	396548327	7903	0	0
CgEnOn_A	396548327	5642	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396548327	7903	0	0
T1	279648	10	0	0
T2	169372	175	0	0
T4	157065	1	0	0
T18	1169	5	0	0
T19	1953	1	0	0
T20	7135	1	0	0
T21	2216	1	0	0
T22	7939	1	0	0
T23	1869	1	0	0
T24	3969	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396548327	5642	0	0
T1	279648	8	0	0
T2	169372	164	0	0
T4	157065	0	0	0
T11	0	47	0	0
T12	0	16	0	0
T18	1169	4	0	0
T19	1953	0	0	0
T20	7135	0	0	0
T21	2216	0	0	0
T22	7939	0	0	0
T23	1869	0	0	0
T24	3969	0	0	0
T68	0	1	0	0
T72	0	11	0	0
T115	0	1	0	0
T152	0	1	0	0
T153	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	203386083	7697	0	0
CgEnOn_A	203386083	5434	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	203386083	7697	0	0
T1	145590	13	0	0
T2	859862	176	0	0
T4	101576	1	0	0
T18	584	3	0	0
T19	976	1	0	0
T20	3568	1	0	0
T21	1108	1	0	0
T22	3969	1	0	0
T23	934	1	0	0
T24	1985	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	203386083	5434	0	0
T1	145590	11	0	0
T2	859862	165	0	0
T4	101576	0	0	0
T11	0	47	0	0
T12	0	14	0	0
T18	584	2	0	0
T19	976	0	0	0
T20	3568	0	0	0
T21	1108	0	0	0
T22	3969	0	0	0
T23	934	0	0	0
T24	1985	0	0	0
T68	0	1	0	0
T72	0	11	0	0
T115	0	1	0	0
T152	0	1	0	0
T153	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T56
1	0	Covered	T1,T2,T22
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	423401940	4133	0	0
CgEnOn_A	423401940	4136	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423401940	4133	0	0
T1	297310	3	0	0
T2	178895	160	0	0
T4	217614	0	0	0
T11	0	30	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7433	0	0	0
T21	2309	0	0	0
T22	8269	3	0	0
T23	1947	0	0	0
T24	4134	4	0	0
T68	0	1	0	0
T70	0	7	0	0
T114	0	5	0	0
T115	0	1	0	0
T116	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423401940	4136	0	0
T1	297310	3	0	0
T2	178895	160	0	0
T4	217614	0	0	0
T11	0	30	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7433	0	0	0
T21	2309	0	0	0
T22	8269	3	0	0
T23	1947	0	0	0
T24	4134	4	0	0
T68	0	1	0	0
T70	0	7	0	0
T114	0	5	0	0
T115	0	1	0	0
T116	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T56
1	0	Covered	T1,T2,T22
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	423401940	4141	0	0
CgEnOn_A	423401940	4142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423401940	4141	0	0
T1	297310	3	0	0
T2	178895	180	0	0
T4	217614	0	0	0
T11	0	34	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7433	0	0	0
T21	2309	0	0	0
T22	8269	3	0	0
T23	1947	0	0	0
T24	4134	4	0	0
T68	0	1	0	0
T70	0	8	0	0
T114	0	4	0	0
T115	0	1	0	0
T116	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423401940	4142	0	0
T1	297310	3	0	0
T2	178895	180	0	0
T4	217614	0	0	0
T11	0	34	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7433	0	0	0
T21	2309	0	0	0
T22	8269	3	0	0
T23	1947	0	0	0
T24	4134	4	0	0
T68	0	1	0	0
T70	0	8	0	0
T114	0	4	0	0
T115	0	1	0	0
T116	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T56
1	0	Covered	T1,T2,T22
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	423401940	4105	0	0
CgEnOn_A	423401940	4107	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423401940	4105	0	0
T1	297310	1	0	0
T2	178895	165	0	0
T4	217614	0	0	0
T11	0	31	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7433	0	0	0
T21	2309	0	0	0
T22	8269	5	0	0
T23	1947	0	0	0
T24	4134	8	0	0
T68	0	1	0	0
T70	0	7	0	0
T114	0	2	0	0
T115	0	1	0	0
T116	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423401940	4107	0	0
T1	297310	1	0	0
T2	178895	165	0	0
T4	217614	0	0	0
T11	0	31	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7433	0	0	0
T21	2309	0	0	0
T22	8269	5	0	0
T23	1947	0	0	0
T24	4134	8	0	0
T68	0	1	0	0
T70	0	7	0	0
T114	0	2	0	0
T115	0	1	0	0
T116	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T56
1	0	Covered	T1,T2,T22
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	423401940	4124	0	0
CgEnOn_A	423401940	4125	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423401940	4124	0	0
T1	297310	2	0	0
T2	178895	166	0	0
T4	217614	0	0	0
T11	0	33	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7433	0	0	0
T21	2309	0	0	0
T22	8269	5	0	0
T23	1947	0	0	0
T24	4134	5	0	0
T68	0	1	0	0
T70	0	6	0	0
T114	0	5	0	0
T115	0	1	0	0
T116	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423401940	4125	0	0
T1	297310	2	0	0
T2	178895	166	0	0
T4	217614	0	0	0
T11	0	33	0	0
T18	1218	0	0	0
T19	2035	0	0	0
T20	7433	0	0	0
T21	2309	0	0	0
T22	8269	5	0	0
T23	1947	0	0	0
T24	4134	5	0	0
T68	0	1	0	0
T70	0	6	0	0
T114	0	5	0	0
T115	0	1	0	0
T116	0	5	0	0