Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T18

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T44,T45,T46
1	1	Covered	T1,T2,T18

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	896124344	14394	0	0
GateOpen_A	896124344	14389	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	896124344	14394	0	0
T1	634845	28	0	0
T2	2299701	435	0	0
T4	376423	0	0	0
T11	0	125	0	0
T12	0	25	0	0
T18	2594	11	0	0
T19	4365	0	0	0
T20	16501	0	0	0
T21	4972	0	0	0
T22	17845	0	0	0
T23	4214	0	0	0
T24	8842	0	0	0
T68	0	4	0	0
T72	0	30	0	0
T115	0	4	0	0
T152	0	3	0	0
T153	0	19	0	0
T154	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	896124344	14389	0	0
T1	634845	28	0	0
T2	2299701	435	0	0
T4	376423	0	0	0
T11	0	125	0	0
T12	0	25	0	0
T18	2594	11	0	0
T19	4365	0	0	0
T20	16501	0	0	0
T21	4972	0	0	0
T22	17845	0	0	0
T23	4214	0	0	0
T24	8842	0	0	0
T68	0	4	0	0
T72	0	30	0	0
T115	0	4	0	0
T152	0	3	0	0
T153	0	19	0	0
T154	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T18

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T44,T45,T46
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	98729437	3511	0	0
GateOpen_A	98729437	3511	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98729437	3511	0	0
T1	69869	7	0	0
T2	423488	112	0	0
T4	39261	0	0	0
T11	0	31	0	0
T12	0	7	0	0
T18	280	2	0	0
T19	478	0	0	0
T20	1932	0	0	0
T21	548	0	0	0
T22	1979	0	0	0
T23	470	0	0	0
T24	963	0	0	0
T68	0	1	0	0
T72	0	7	0	0
T115	0	1	0	0
T153	0	4	0	0
T154	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98729437	3511	0	0
T1	69869	7	0	0
T2	423488	112	0	0
T4	39261	0	0	0
T11	0	31	0	0
T12	0	7	0	0
T18	280	2	0	0
T19	478	0	0	0
T20	1932	0	0	0
T21	548	0	0	0
T22	1979	0	0	0
T23	470	0	0	0
T24	963	0	0	0
T68	0	1	0	0
T72	0	7	0	0
T115	0	1	0	0
T153	0	4	0	0
T154	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T18

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T44,T45,T46
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	197459659	3648	0	0
GateOpen_A	197459659	3646	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197459659	3648	0	0
T1	139737	7	0	0
T2	846979	104	0	0
T4	78521	0	0	0
T11	0	29	0	0
T12	0	5	0	0
T18	559	2	0	0
T19	956	0	0	0
T20	3865	0	0	0
T21	1099	0	0	0
T22	3958	0	0	0
T23	940	0	0	0
T24	1925	0	0	0
T68	0	1	0	0
T72	0	8	0	0
T115	0	1	0	0
T152	0	1	0	0
T153	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197459659	3646	0	0
T1	139737	7	0	0
T2	846979	104	0	0
T4	78521	0	0	0
T11	0	29	0	0
T12	0	5	0	0
T18	559	2	0	0
T19	956	0	0	0
T20	3865	0	0	0
T21	1099	0	0	0
T22	3958	0	0	0
T23	940	0	0	0
T24	1925	0	0	0
T68	0	1	0	0
T72	0	8	0	0
T115	0	1	0	0
T152	0	1	0	0
T153	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T18

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T44,T45,T46
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	396548768	3653	0	0
GateOpen_A	396548768	3652	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396548768	3653	0	0
T1	279648	6	0	0
T2	169372	113	0	0
T4	157065	0	0	0
T11	0	33	0	0
T12	0	7	0	0
T18	1170	3	0	0
T19	1954	0	0	0
T20	7136	0	0	0
T21	2217	0	0	0
T22	7939	0	0	0
T23	1869	0	0	0
T24	3969	0	0	0
T68	0	1	0	0
T72	0	7	0	0
T115	0	1	0	0
T152	0	1	0	0
T153	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396548768	3652	0	0
T1	279648	6	0	0
T2	169372	113	0	0
T4	157065	0	0	0
T11	0	33	0	0
T12	0	7	0	0
T18	1170	3	0	0
T19	1954	0	0	0
T20	7136	0	0	0
T21	2217	0	0	0
T22	7939	0	0	0
T23	1869	0	0	0
T24	3969	0	0	0
T68	0	1	0	0
T72	0	7	0	0
T115	0	1	0	0
T152	0	1	0	0
T153	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T18

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T44,T45,T46
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	203386480	3582	0	0
GateOpen_A	203386480	3580	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	203386480	3582	0	0
T1	145591	8	0	0
T2	859862	106	0	0
T4	101576	0	0	0
T11	0	32	0	0
T12	0	6	0	0
T18	585	4	0	0
T19	977	0	0	0
T20	3568	0	0	0
T21	1108	0	0	0
T22	3969	0	0	0
T23	935	0	0	0
T24	1985	0	0	0
T68	0	1	0	0
T72	0	8	0	0
T115	0	1	0	0
T152	0	1	0	0
T153	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	203386480	3580	0	0
T1	145591	8	0	0
T2	859862	106	0	0
T4	101576	0	0	0
T11	0	32	0	0
T12	0	6	0	0
T18	585	4	0	0
T19	977	0	0	0
T20	3568	0	0	0
T21	1108	0	0	0
T22	3969	0	0	0
T23	935	0	0	0
T24	1985	0	0	0
T68	0	1	0	0
T72	0	8	0	0
T115	0	1	0	0
T152	0	1	0	0
T153	0	5	0	0