Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	488430	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2768215

1

T4

13

T5

6

T6

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	797576	1			T4	10		T6	15		T21	2
values[0x0]	1129418	1			T4	17		T5	21		T6	19
values[0x1]	1329651	1			T4	4		T5	18		T6	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	270362	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2986283

1

T4

18

T5

7

T6

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13459	1			T21	1		T2	437		T17	1
valid_sources[0x01]	12754	1			T1	2		T2	442		T8	5
valid_sources[0x02]	13542	1			T1	2		T2	421		T22	1
valid_sources[0x03]	12163	1			T1	3		T2	499		T17	1
valid_sources[0x04]	12457	1			T2	416		T8	6		T22	1
valid_sources[0x05]	11988	1			T1	4		T2	517		T8	8
valid_sources[0x06]	12807	1			T4	1		T6	4		T1	2
valid_sources[0x07]	12731	1			T1	3		T2	486		T8	2
valid_sources[0x08]	13056	1			T4	1		T1	2		T2	395
valid_sources[0x09]	12176	1			T1	4		T2	418		T8	7
valid_sources[0x0a]	12486	1			T1	3		T2	439		T8	13
valid_sources[0x0b]	12297	1			T2	453		T8	3		T96	1
valid_sources[0x0c]	13655	1			T1	1		T2	445		T8	6
valid_sources[0x0d]	12720	1			T1	2		T2	473		T8	5
valid_sources[0x0e]	12173	1			T4	1		T2	447		T8	4
valid_sources[0x0f]	13164	1			T2	487		T8	6		T97	1
valid_sources[0x10]	13817	1			T1	3		T2	387		T17	2
valid_sources[0x11]	11523	1			T1	1		T2	415		T8	8
valid_sources[0x12]	11410	1			T2	476		T8	3		T65	3
valid_sources[0x13]	13059	1			T4	1		T1	2		T2	531
valid_sources[0x14]	13181	1			T6	8		T1	2		T2	459
valid_sources[0x15]	12532	1			T5	2		T2	440		T8	3
valid_sources[0x16]	14013	1			T1	3		T2	410		T17	1
valid_sources[0x17]	12926	1			T2	375		T8	1		T96	2
valid_sources[0x18]	12876	1			T2	404		T8	5		T97	3
valid_sources[0x19]	13254	1			T1	3		T2	486		T8	10
valid_sources[0x1a]	12485	1			T2	449		T8	14		T19	1
valid_sources[0x1b]	12536	1			T2	438		T8	3		T9	6
valid_sources[0x1c]	11325	1			T2	487		T8	9		T97	1
valid_sources[0x1d]	12311	1			T4	1		T1	1		T2	450
valid_sources[0x1e]	12431	1			T6	4		T1	2		T2	467
valid_sources[0x1f]	12426	1			T2	382		T8	6		T27	6
valid_sources[0x20]	11730	1			T1	3		T2	536		T8	13
valid_sources[0x21]	13435	1			T4	1		T1	2		T2	408
valid_sources[0x22]	11842	1			T2	457		T8	9		T97	2
valid_sources[0x23]	13085	1			T4	1		T6	4		T1	4
valid_sources[0x24]	12686	1			T1	3		T2	446		T8	7
valid_sources[0x25]	12182	1			T4	1		T2	435		T8	12
valid_sources[0x26]	13254	1			T2	471		T8	6		T65	10
valid_sources[0x27]	12095	1			T2	427		T8	5		T20	1
valid_sources[0x28]	13099	1			T1	3		T2	399		T17	2
valid_sources[0x29]	13442	1			T2	434		T8	14		T27	3
valid_sources[0x2a]	12109	1			T1	1		T2	397		T8	6
valid_sources[0x2b]	13285	1			T5	1		T2	408		T8	7
valid_sources[0x2c]	12826	1			T1	2		T2	457		T8	12
valid_sources[0x2d]	13603	1			T1	3		T2	444		T17	1
valid_sources[0x2e]	11175	1			T2	451		T8	4		T167	1
valid_sources[0x2f]	11862	1			T5	2		T1	2		T2	500
valid_sources[0x30]	11863	1			T1	6		T2	413		T8	5
valid_sources[0x31]	12318	1			T1	2		T2	418		T8	7
valid_sources[0x32]	12280	1			T2	500		T8	4		T22	2
valid_sources[0x33]	12197	1			T1	1		T2	489		T17	1
valid_sources[0x34]	12720	1			T1	2		T2	488		T8	7
valid_sources[0x35]	11798	1			T4	1		T6	7		T1	3
valid_sources[0x36]	13216	1			T5	1		T2	518		T8	2
valid_sources[0x37]	12571	1			T4	1		T2	466		T8	9
valid_sources[0x38]	11562	1			T4	1		T1	2		T2	471
valid_sources[0x39]	13204	1			T4	1		T1	3		T2	450
valid_sources[0x3a]	12804	1			T1	1		T2	459		T8	1
valid_sources[0x3b]	12348	1			T2	464		T8	5		T65	2
valid_sources[0x3c]	12651	1			T6	4		T1	1		T2	430
valid_sources[0x3d]	11817	1			T1	1		T2	429		T8	6
valid_sources[0x3e]	12405	1			T5	1		T2	457		T17	2
valid_sources[0x3f]	12438	1			T2	446		T8	11		T22	2
valid_sources[0x40]	12529	1			T2	419		T8	6		T96	1
valid_sources[0x41]	11889	1			T1	3		T2	518		T8	8
valid_sources[0x42]	13964	1			T21	1		T2	467		T8	4
valid_sources[0x43]	12644	1			T1	1		T2	501		T17	2
valid_sources[0x44]	12353	1			T1	2		T2	459		T8	5
valid_sources[0x45]	14123	1			T1	1		T2	411		T17	2
valid_sources[0x46]	12306	1			T1	3		T2	447		T8	2
valid_sources[0x47]	12040	1			T5	1		T1	3		T2	481
valid_sources[0x48]	12677	1			T5	1		T15	28		T2	430
valid_sources[0x49]	11811	1			T5	2		T1	6		T2	396
valid_sources[0x4a]	11798	1			T1	3		T2	438		T8	1
valid_sources[0x4b]	13358	1			T1	5		T2	417		T8	4
valid_sources[0x4c]	12483	1			T1	3		T2	439		T8	6
valid_sources[0x4d]	12115	1			T1	6		T2	513		T17	1
valid_sources[0x4e]	12438	1			T1	1		T2	444		T8	5
valid_sources[0x4f]	14001	1			T5	1		T6	7		T1	1
valid_sources[0x50]	12640	1			T2	492		T17	4		T8	5
valid_sources[0x51]	14011	1			T1	3		T2	414		T8	2
valid_sources[0x52]	13342	1			T1	4		T2	449		T8	1
valid_sources[0x53]	12756	1			T1	1		T2	426		T8	3
valid_sources[0x54]	12274	1			T2	504		T8	6		T22	1
valid_sources[0x55]	12384	1			T1	5		T2	468		T8	8
valid_sources[0x56]	12744	1			T5	1		T1	7		T2	467
valid_sources[0x57]	12324	1			T1	5		T2	505		T8	11
valid_sources[0x58]	12926	1			T2	440		T17	2		T8	11
valid_sources[0x59]	12362	1			T4	1		T1	5		T2	445
valid_sources[0x5a]	13393	1			T1	2		T2	496		T8	7
valid_sources[0x5b]	14135	1			T1	1		T2	465		T17	1
valid_sources[0x5c]	12956	1			T2	422		T8	5		T27	1
valid_sources[0x5d]	13563	1			T2	463		T8	6		T64	11
valid_sources[0x5e]	13112	1			T1	2		T2	475		T8	3
valid_sources[0x5f]	12575	1			T2	457		T8	8		T65	4
valid_sources[0x60]	13506	1			T4	1		T2	519		T8	4
valid_sources[0x61]	12298	1			T1	3		T2	449		T8	1
valid_sources[0x62]	12958	1			T1	2		T2	552		T16	52
valid_sources[0x63]	12810	1			T1	2		T2	466		T8	8
valid_sources[0x64]	16217	1			T2	428		T8	2		T97	1
valid_sources[0x65]	12655	1			T1	3		T2	431		T8	11
valid_sources[0x66]	11946	1			T2	417		T8	2		T96	1
valid_sources[0x67]	12085	1			T2	461		T8	7		T27	1
valid_sources[0x68]	12115	1			T2	404		T8	6		T9	1
valid_sources[0x69]	13630	1			T1	4		T2	467		T17	1
valid_sources[0x6a]	14201	1			T2	472		T8	4		T22	1
valid_sources[0x6b]	13690	1			T1	2		T2	388		T17	1
valid_sources[0x6c]	12816	1			T1	4		T2	478		T17	1
valid_sources[0x6d]	12046	1			T2	464		T8	4		T101	3
valid_sources[0x6e]	13128	1			T1	2		T2	427		T8	9
valid_sources[0x6f]	12892	1			T1	1		T2	444		T8	9
valid_sources[0x70]	13978	1			T1	5		T2	490		T8	13
valid_sources[0x71]	12453	1			T1	1		T2	428		T8	6
valid_sources[0x72]	13092	1			T1	1		T2	462		T8	6
valid_sources[0x73]	12884	1			T1	1		T2	512		T8	3
valid_sources[0x74]	13161	1			T1	1		T2	468		T8	6
valid_sources[0x75]	15024	1			T1	1		T2	492		T8	8
valid_sources[0x76]	13755	1			T2	438		T8	10		T22	1
valid_sources[0x77]	13701	1			T4	1		T1	1		T2	482
valid_sources[0x78]	15049	1			T1	2		T2	464		T17	1
valid_sources[0x79]	13002	1			T1	2		T2	435		T8	1
valid_sources[0x7a]	11774	1			T2	408		T17	1		T8	3
valid_sources[0x7b]	13333	1			T1	4		T2	420		T17	1
valid_sources[0x7c]	12186	1			T5	1		T1	1		T2	478
valid_sources[0x7d]	13106	1			T2	489		T8	3		T97	1
valid_sources[0x7e]	13417	1			T1	2		T2	436		T8	7
valid_sources[0x7f]	12351	1			T1	2		T2	444		T8	8
valid_sources[0x80]	12565	1			T1	1		T2	477		T8	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

697078

1

T4

6

T6

10

T1

16

values[0x0]

all_enables

biggest_size

1053872

1

T4

6

T5

4

T6

5

values[0x1]

all_enables

biggest_size

1017265

1

T4

1

T5

2

T6

3