Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	660754150	58673	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660754150	58673	0	0
T1	563100	200	0	0
T2	2163785	1972	0	0
T3	112770	30	0	0
T8	1851295	125	0	0
T9	0	135	0	0
T10	0	63	0	0
T11	0	49	0	0
T12	0	112	0	0
T13	0	1034	0	0
T14	0	251	0	0
T15	7970	0	0	0
T16	10700	0	0	0
T17	8440	0	0	0
T18	9780	0	0	0
T19	6390	0	0	0
T20	3865	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	132150830	8837	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	8837	0	0
T1	112620	29	0	0
T2	432757	284	0	0
T3	22554	6	0	0
T8	370259	18	0	0
T9	0	20	0	0
T10	0	12	0	0
T11	0	8	0	0
T12	0	15	0	0
T13	0	159	0	0
T14	0	41	0	0
T15	1594	0	0	0
T16	2140	0	0	0
T17	1688	0	0	0
T18	1956	0	0	0
T19	1278	0	0	0
T20	773	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	132150830	11756	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	11756	0	0
T1	112620	40	0	0
T2	432757	392	0	0
T3	22554	6	0	0
T8	370259	26	0	0
T9	0	27	0	0
T10	0	12	0	0
T11	0	10	0	0
T12	0	22	0	0
T13	0	212	0	0
T14	0	51	0	0
T15	1594	0	0	0
T16	2140	0	0	0
T17	1688	0	0	0
T18	1956	0	0	0
T19	1278	0	0	0
T20	773	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	132150830	17497	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	17497	0	0
T1	112620	61	0	0
T2	432757	615	0	0
T3	22554	6	0	0
T8	370259	38	0	0
T9	0	41	0	0
T10	0	15	0	0
T11	0	13	0	0
T12	0	36	0	0
T13	0	305	0	0
T14	0	69	0	0
T15	1594	0	0	0
T16	2140	0	0	0
T17	1688	0	0	0
T18	1956	0	0	0
T19	1278	0	0	0
T20	773	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	132150830	8736	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	8736	0	0
T1	112620	29	0	0
T2	432757	281	0	0
T3	22554	6	0	0
T8	370259	18	0	0
T9	0	20	0	0
T10	0	12	0	0
T11	0	8	0	0
T12	0	16	0	0
T13	0	156	0	0
T14	0	40	0	0
T15	1594	0	0	0
T16	2140	0	0	0
T17	1688	0	0	0
T18	1956	0	0	0
T19	1278	0	0	0
T20	773	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	132150830	11847	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	11847	0	0
T1	112620	41	0	0
T2	432757	400	0	0
T3	22554	6	0	0
T8	370259	25	0	0
T9	0	27	0	0
T10	0	12	0	0
T11	0	10	0	0
T12	0	23	0	0
T13	0	202	0	0
T14	0	50	0	0
T15	1594	0	0	0
T16	2140	0	0	0
T17	1688	0	0	0
T18	1956	0	0	0
T19	1278	0	0	0
T20	773	0	0	0