Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T2,T3,T8

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	132150830	130474596	0	0
AllClkBypReqTrue_A	132150830	116371	0	0
IoClkBypReqFalse_A	132150830	130409712	0	1893
IoClkBypReqTrue_A	132150830	177897	0	0
LcClkBypAckFalse_A	132150830	130485549	0	0
LcClkBypAckTrue_A	132150830	105418	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	130474596	0	0
T1	112620	112527	0	0
T2	432757	430279	0	0
T3	22554	22193	0	0
T4	1639	1498	0	0
T5	1318	1273	0	0
T6	2328	1947	0	0
T15	1594	1448	0	0
T16	2140	2037	0	0
T17	1688	1664	0	0
T21	800	781	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	116371	0	0
T1	112620	0	0	0
T2	432757	4570	0	0
T3	22554	317	0	0
T4	1639	126	0	0
T5	1318	0	0	0
T6	2328	154	0	0
T8	0	460	0	0
T15	1594	65	0	0
T16	2140	53	0	0
T17	1688	0	0	0
T19	0	37	0	0
T21	800	0	0	0
T27	0	710	0	0
T101	0	419	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	130409712	0	1893
T1	112620	112525	0	3
T2	432757	430058	0	3
T3	22554	22147	0	3
T4	1639	1428	0	3
T5	1318	1271	0	3
T6	2328	2099	0	3
T15	1594	1511	0	3
T16	2140	2088	0	3
T17	1688	1662	0	3
T21	800	711	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	177897	0	0
T1	112620	0	0	0
T2	432757	6759	0	0
T3	22554	355	0	0
T4	1639	194	0	0
T5	1318	0	0	0
T6	2328	0	0	0
T8	0	599	0	0
T9	0	137	0	0
T15	1594	0	0	0
T16	2140	0	0	0
T17	1688	0	0	0
T21	800	68	0	0
T27	0	862	0	0
T82	0	27	0	0
T83	0	214	0	0
T101	0	343	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	130485549	0	0
T1	112620	112527	0	0
T2	432757	430355	0	0
T3	22554	22182	0	0
T4	1639	1506	0	0
T5	1318	1273	0	0
T6	2328	2101	0	0
T15	1594	1513	0	0
T16	2140	2090	0	0
T17	1688	1664	0	0
T21	800	781	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	105418	0	0
T1	112620	0	0	0
T2	432757	3814	0	0
T3	22554	328	0	0
T4	1639	118	0	0
T5	1318	0	0	0
T6	2328	0	0	0
T8	0	301	0	0
T9	0	118	0	0
T15	1594	0	0	0
T16	2140	0	0	0
T17	1688	0	0	0
T21	800	0	0	0
T27	0	441	0	0
T82	0	24	0	0
T83	0	106	0	0
T84	0	233	0	0
T101	0	88	0	0