Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	12500	0	0
TransStop_A	2147483647	6421	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12500	0	0
T2	3470280	238	0	0
T3	1804360	32	0	0
T8	2842080	7	0	0
T16	12064	0	0	0
T17	51944	20	0	0
T18	46052	29	0	0
T19	20468	0	0	0
T20	18216	0	0	0
T27	0	100	0	0
T64	6916	0	0	0
T65	24072	26	0	0
T96	0	4	0	0
T97	0	44	0	0
T113	0	33	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6421	0	0
T2	3470280	113	0	0
T3	1804360	21	0	0
T8	2842080	5	0	0
T16	12064	0	0	0
T17	51944	10	0	0
T18	46052	18	0	0
T19	20468	0	0	0
T20	18216	0	0	0
T27	0	56	0	0
T64	6916	0	0	0
T65	24072	14	0	0
T96	0	4	0	0
T97	0	20	0	0
T113	0	18	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	549107971	3102	0	0
TransStop_A	549107971	1607	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107971	3102	0	0
T2	867570	61	0	0
T3	451090	8	0	0
T8	710520	1	0	0
T16	3016	0	0	0
T17	12986	5	0	0
T18	11513	9	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	24	0	0
T64	1729	0	0	0
T65	6018	7	0	0
T96	0	1	0	0
T97	0	13	0	0
T113	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107971	1607	0	0
T2	867570	29	0	0
T3	451090	5	0	0
T8	710520	1	0	0
T16	3016	0	0	0
T17	12986	2	0	0
T18	11513	6	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	14	0	0
T64	1729	0	0	0
T65	6018	3	0	0
T96	0	1	0	0
T97	0	7	0	0
T113	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	549107971	3111	0	0
TransStop_A	549107971	1615	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107971	3111	0	0
T2	867570	67	0	0
T3	451090	8	0	0
T8	710520	1	0	0
T16	3016	0	0	0
T17	12986	3	0	0
T18	11513	5	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	26	0	0
T64	1729	0	0	0
T65	6018	7	0	0
T96	0	1	0	0
T97	0	9	0	0
T113	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107971	1615	0	0
T2	867570	32	0	0
T3	451090	5	0	0
T8	710520	1	0	0
T16	3016	0	0	0
T17	12986	2	0	0
T18	11513	3	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	14	0	0
T64	1729	0	0	0
T65	6018	4	0	0
T96	0	1	0	0
T97	0	5	0	0
T113	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	549107971	3154	0	0
TransStop_A	549107971	1599	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107971	3154	0	0
T2	867570	50	0	0
T3	451090	9	0	0
T8	710520	3	0	0
T16	3016	0	0	0
T17	12986	7	0	0
T18	11513	8	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	25	0	0
T64	1729	0	0	0
T65	6018	8	0	0
T96	0	1	0	0
T97	0	9	0	0
T113	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107971	1599	0	0
T2	867570	25	0	0
T3	451090	5	0	0
T8	710520	2	0	0
T16	3016	0	0	0
T17	12986	4	0	0
T18	11513	5	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	15	0	0
T64	1729	0	0	0
T65	6018	4	0	0
T96	0	1	0	0
T97	0	2	0	0
T113	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	549107971	3133	0	0
TransStop_A	549107971	1600	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107971	3133	0	0
T2	867570	60	0	0
T3	451090	7	0	0
T8	710520	2	0	0
T16	3016	0	0	0
T17	12986	5	0	0
T18	11513	7	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	25	0	0
T64	1729	0	0	0
T65	6018	4	0	0
T96	0	1	0	0
T97	0	13	0	0
T113	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107971	1600	0	0
T2	867570	27	0	0
T3	451090	6	0	0
T8	710520	1	0	0
T16	3016	0	0	0
T17	12986	2	0	0
T18	11513	4	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	13	0	0
T64	1729	0	0	0
T65	6018	3	0	0
T96	0	1	0	0
T97	0	6	0	0
T113	0	4	0	0