Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	132836291	4061598	0	0
clk_enables_rd_A	132836291	46227	0	0
clk_hints_rd_A	132836291	40714	0	0
extclk_ctrl_rd_A	132836291	52669	0	0
extclk_ctrl_regwen_rd_A	132836291	39479	0	0
jitter_enable_rd_A	132836291	58698	0	0
jitter_regwen_rd_A	132836291	45190	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132836291	4061598	0	0
T2	432757	153037	0	0
T3	22554	0	0	0
T8	370259	0	0	0
T13	0	73809	0	0
T16	2140	0	0	0
T17	1688	0	0	0
T18	1956	0	0	0
T19	1278	0	0	0
T20	773	0	0	0
T23	0	129793	0	0
T24	0	124405	0	0
T25	0	60933	0	0
T59	0	59673	0	0
T60	0	118042	0	0
T61	0	93365	0	0
T62	0	73418	0	0
T63	0	79347	0	0
T64	847	0	0	0
T65	2648	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132836291	46227	0	0
T8	370259	8	0	0
T13	0	1411	0	0
T14	0	9	0	0
T18	1956	0	0	0
T19	1278	0	0	0
T20	773	0	0	0
T22	53592	0	0	0
T23	0	4691	0	0
T24	0	2495	0	0
T27	0	1	0	0
T64	847	0	0	0
T65	2648	0	0	0
T96	1515	8	0	0
T97	3284	0	0	0
T101	1939	0	0	0
T136	0	5	0	0
T137	0	3	0	0
T138	0	6	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132836291	40714	0	0
T3	22554	7	0	0
T8	370259	4	0	0
T13	0	1271	0	0
T14	0	7	0	0
T17	1688	0	0	0
T18	1956	0	0	0
T19	1278	0	0	0
T20	773	0	0	0
T22	53592	0	0	0
T23	0	4406	0	0
T24	0	2084	0	0
T27	0	1	0	0
T64	847	0	0	0
T65	2648	0	0	0
T96	1515	3	0	0
T136	0	9	0	0
T137	0	7	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132836291	52669	0	0
T1	112620	0	0	0
T2	432757	0	0	0
T3	22554	30	0	0
T6	2328	41	0	0
T8	370259	68	0	0
T13	0	1809	0	0
T14	0	34	0	0
T15	1594	0	0	0
T16	2140	0	0	0
T17	1688	0	0	0
T18	1956	0	0	0
T21	800	0	0	0
T23	0	5282	0	0
T27	0	66	0	0
T83	0	25	0	0
T84	0	53	0	0
T101	0	27	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132836291	39479	0	0
T13	234000	1324	0	0
T14	182920	0	0	0
T23	0	4057	0	0
T24	0	2361	0	0
T34	0	2553	0	0
T43	0	5	0	0
T45	0	3	0	0
T62	0	2479	0	0
T67	13897	0	0	0
T68	66551	0	0	0
T110	0	37	0	0
T139	0	29	0	0
T140	0	18	0	0
T141	2132	0	0	0
T142	885	0	0	0
T143	1623	0	0	0
T144	1381	0	0	0
T145	1351	0	0	0
T146	2069	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132836291	58698	0	0
T3	22554	120	0	0
T8	370259	110	0	0
T13	0	1735	0	0
T14	0	371	0	0
T17	1688	0	0	0
T18	1956	0	0	0
T19	1278	0	0	0
T20	773	0	0	0
T22	53592	0	0	0
T23	0	5704	0	0
T24	0	3278	0	0
T27	0	86	0	0
T64	847	0	0	0
T65	2648	0	0	0
T96	1515	74	0	0
T136	0	103	0	0
T137	0	130	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132836291	45190	0	0
T13	234000	1544	0	0
T14	182920	0	0	0
T23	0	4961	0	0
T24	0	2535	0	0
T34	0	2796	0	0
T62	0	3123	0	0
T67	13897	0	0	0
T68	66551	0	0	0
T141	2132	0	0	0
T142	885	0	0	0
T143	1623	0	0	0
T144	1381	0	0	0
T145	1351	0	0	0
T146	2069	0	0	0
T147	0	2064	0	0
T148	0	3480	0	0
T149	0	1925	0	0
T150	0	2719	0	0
T151	0	1259	0	0