Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	132150830	121	0	0
IoStatusRise_A	132150830	121	0	0
MainStatusFall_A	132150830	127	0	0
MainStatusRise_A	132150830	127	0	0
UsbStatusFall_A	132150830	121	0	0
UsbStatusRise_A	132150830	121	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	121	0	0
T9	234961	0	0	0
T10	14333	0	0	0
T29	11618	0	0	0
T30	1396	0	0	0
T31	761	0	0	0
T35	794	2	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T50	9137	0	0	0
T82	1480	0	0	0
T113	2902	0	0	0
T142	0	4	0	0
T152	0	6	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	1	0	0
T157	1462	0	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	121	0	0
T9	234961	0	0	0
T10	14333	0	0	0
T29	11618	0	0	0
T30	1396	0	0	0
T31	761	0	0	0
T35	794	2	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T50	9137	0	0	0
T82	1480	0	0	0
T113	2902	0	0	0
T142	0	4	0	0
T152	0	6	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	1	0	0
T157	1462	0	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	127	0	0
T9	234961	0	0	0
T10	14333	0	0	0
T29	11618	0	0	0
T30	1396	0	0	0
T31	761	0	0	0
T35	794	2	0	0
T36	0	5	0	0
T37	0	4	0	0
T50	9137	0	0	0
T82	1480	0	0	0
T113	2902	0	0	0
T142	0	4	0	0
T152	0	5	0	0
T153	0	5	0	0
T154	0	2	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	1462	0	0	0
T158	0	3	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	127	0	0
T9	234961	0	0	0
T10	14333	0	0	0
T29	11618	0	0	0
T30	1396	0	0	0
T31	761	0	0	0
T35	794	2	0	0
T36	0	5	0	0
T37	0	4	0	0
T50	9137	0	0	0
T82	1480	0	0	0
T113	2902	0	0	0
T142	0	4	0	0
T152	0	5	0	0
T153	0	5	0	0
T154	0	2	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	1462	0	0	0
T158	0	3	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	121	0	0
T11	4315	0	0	0
T12	91502	0	0	0
T36	1751	5	0	0
T37	1437	4	0	0
T38	1273	1	0	0
T66	13305	0	0	0
T84	2164	0	0	0
T142	0	3	0	0
T152	0	5	0	0
T153	0	4	0	0
T154	0	3	0	0
T155	0	4	0	0
T156	0	1	0	0
T158	0	4	0	0
T159	2411	0	0	0
T160	74404	0	0	0
T161	1972	0	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132150830	121	0	0
T11	4315	0	0	0
T12	91502	0	0	0
T36	1751	5	0	0
T37	1437	4	0	0
T38	1273	1	0	0
T66	13305	0	0	0
T84	2164	0	0	0
T142	0	3	0	0
T152	0	5	0	0
T153	0	4	0	0
T154	0	3	0	0
T155	0	4	0	0
T156	0	1	0	0
T158	0	4	0	0
T159	2411	0	0	0
T160	74404	0	0	0
T161	1972	0	0	0