Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	38330	0	0
CgEnOn_A	2147483647	31632	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38330	0	0
T1	378345	3	0	0
T2	2307344	409	0	0
T3	1214193	152	0	0
T4	31785	3	0	0
T5	3494	47	0	0
T6	3914	3	0	0
T8	710519	1	0	0
T9	880119	0	0	0
T10	343867	0	0	0
T15	5625	3	0	0
T16	8112	3	0	0
T17	34759	8	0	0
T21	12207	3	0	0
T29	213905	0	0	0
T30	4911	0	0	0
T31	7435	0	0	0
T35	10304	12	0	0
T36	0	20	0	0
T37	0	15	0	0
T38	0	5	0	0
T50	28196	0	0	0
T82	3315	0	0	0
T113	27135	0	0	0
T142	0	20	0	0
T152	0	30	0	0
T153	0	15	0	0
T154	0	10	0	0
T155	0	25	0	0
T156	0	5	0	0
T157	6310	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31632	0	0
T1	378345	0	0	0
T2	2307344	376	0	0
T3	1214193	140	0	0
T5	3494	44	0	0
T6	3914	0	0	0
T8	1742981	77	0	0
T9	880119	39	0	0
T10	343867	0	0	0
T15	5625	0	0	0
T16	8112	0	0	0
T17	34759	5	0	0
T18	11513	9	0	0
T20	0	30	0	0
T21	12207	0	0	0
T27	0	27	0	0
T29	213905	0	0	0
T30	4911	0	0	0
T31	7435	0	0	0
T35	10304	18	0	0
T36	0	20	0	0
T37	0	15	0	0
T38	0	5	0	0
T50	28196	0	0	0
T64	0	22	0	0
T82	3315	0	0	0
T96	0	4	0	0
T113	27135	0	0	0
T142	0	20	0	0
T152	0	30	0	0
T153	0	15	0	0
T154	0	10	0	0
T155	0	25	0	0
T156	0	5	0	0
T157	6310	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	258648079	125	0	0
CgEnOn_A	258648079	125	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	258648079	125	0	0
T9	195571	0	0	0
T10	76394	0	0	0
T29	47514	0	0	0
T30	1086	0	0	0
T31	1644	0	0	0
T35	2266	2	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T50	4118	0	0	0
T82	734	0	0	0
T113	6009	0	0	0
T142	0	4	0	0
T152	0	6	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	1	0	0
T157	1379	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	258648079	125	0	0
T9	195571	0	0	0
T10	76394	0	0	0
T29	47514	0	0	0
T30	1086	0	0	0
T31	1644	0	0	0
T35	2266	2	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T50	4118	0	0	0
T82	734	0	0	0
T113	6009	0	0	0
T142	0	4	0	0
T152	0	6	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	1	0	0
T157	1379	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	129323556	125	0	0
CgEnOn_A	129323556	125	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129323556	125	0	0
T9	97784	0	0	0
T10	38197	0	0	0
T29	23757	0	0	0
T30	543	0	0	0
T31	822	0	0	0
T35	1133	2	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T50	2059	0	0	0
T82	367	0	0	0
T113	3005	0	0	0
T142	0	4	0	0
T152	0	6	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	1	0	0
T157	689	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129323556	125	0	0
T9	97784	0	0	0
T10	38197	0	0	0
T29	23757	0	0	0
T30	543	0	0	0
T31	822	0	0	0
T35	1133	2	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T50	2059	0	0	0
T82	367	0	0	0
T113	3005	0	0	0
T142	0	4	0	0
T152	0	6	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	1	0	0
T157	689	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	518222652	125	0	0
CgEnOn_A	518222652	121	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518222652	125	0	0
T9	391196	0	0	0
T10	152882	0	0	0
T29	95120	0	0	0
T30	2196	0	0	0
T31	3325	0	0	0
T35	4639	2	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T50	17901	0	0	0
T82	1480	0	0	0
T113	12111	0	0	0
T142	0	4	0	0
T152	0	6	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	1	0	0
T157	2864	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518222652	121	0	0
T9	391196	0	0	0
T10	152882	0	0	0
T29	95120	0	0	0
T30	2196	0	0	0
T31	3325	0	0	0
T35	4639	2	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T50	17901	0	0	0
T82	1480	0	0	0
T113	12111	0	0	0
T142	0	4	0	0
T152	0	6	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	1	0	0
T157	2864	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	549107635	128	0	0
CgEnOn_A	549107635	127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107635	128	0	0
T9	461508	0	0	0
T10	159256	0	0	0
T29	129087	0	0	0
T30	2288	0	0	0
T31	3463	0	0	0
T35	4820	2	0	0
T36	0	5	0	0
T37	0	4	0	0
T50	18647	0	0	0
T82	1542	0	0	0
T113	12615	0	0	0
T142	0	4	0	0
T152	0	5	0	0
T153	0	5	0	0
T154	0	2	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	2984	0	0	0
T158	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107635	127	0	0
T9	461508	0	0	0
T10	159256	0	0	0
T29	129087	0	0	0
T30	2288	0	0	0
T31	3463	0	0	0
T35	4820	2	0	0
T36	0	5	0	0
T37	0	4	0	0
T50	18647	0	0	0
T82	1542	0	0	0
T113	12615	0	0	0
T142	0	4	0	0
T152	0	5	0	0
T153	0	5	0	0
T154	0	2	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	2984	0	0	0
T158	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	129323556	125	0	0
CgEnOn_A	129323556	125	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129323556	125	0	0
T9	97784	0	0	0
T10	38197	0	0	0
T29	23757	0	0	0
T30	543	0	0	0
T31	822	0	0	0
T35	1133	2	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T50	2059	0	0	0
T82	367	0	0	0
T113	3005	0	0	0
T142	0	4	0	0
T152	0	6	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	1	0	0
T157	689	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129323556	125	0	0
T9	97784	0	0	0
T10	38197	0	0	0
T29	23757	0	0	0
T30	543	0	0	0
T31	822	0	0	0
T35	1133	2	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T50	2059	0	0	0
T82	367	0	0	0
T113	3005	0	0	0
T142	0	4	0	0
T152	0	6	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	1	0	0
T157	689	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	549107635	128	0	0
CgEnOn_A	549107635	127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107635	128	0	0
T9	461508	0	0	0
T10	159256	0	0	0
T29	129087	0	0	0
T30	2288	0	0	0
T31	3463	0	0	0
T35	4820	2	0	0
T36	0	5	0	0
T37	0	4	0	0
T50	18647	0	0	0
T82	1542	0	0	0
T113	12615	0	0	0
T142	0	4	0	0
T152	0	5	0	0
T153	0	5	0	0
T154	0	2	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	2984	0	0	0
T158	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107635	127	0	0
T9	461508	0	0	0
T10	159256	0	0	0
T29	129087	0	0	0
T30	2288	0	0	0
T31	3463	0	0	0
T35	4820	2	0	0
T36	0	5	0	0
T37	0	4	0	0
T50	18647	0	0	0
T82	1542	0	0	0
T113	12615	0	0	0
T142	0	4	0	0
T152	0	5	0	0
T153	0	5	0	0
T154	0	2	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	2984	0	0	0
T158	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	129323556	125	0	0
CgEnOn_A	129323556	125	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129323556	125	0	0
T9	97784	0	0	0
T10	38197	0	0	0
T29	23757	0	0	0
T30	543	0	0	0
T31	822	0	0	0
T35	1133	2	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T50	2059	0	0	0
T82	367	0	0	0
T113	3005	0	0	0
T142	0	4	0	0
T152	0	6	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	1	0	0
T157	689	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129323556	125	0	0
T9	97784	0	0	0
T10	38197	0	0	0
T29	23757	0	0	0
T30	543	0	0	0
T31	822	0	0	0
T35	1133	2	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T50	2059	0	0	0
T82	367	0	0	0
T113	3005	0	0	0
T142	0	4	0	0
T152	0	6	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	1	0	0
T157	689	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	258648079	6126	0	0
CgEnOn_A	258648079	4452	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	258648079	6126	0	0
T1	108080	1	0	0
T2	411151	114	0	0
T3	220048	49	0	0
T4	9534	1	0	0
T5	991	14	0	0
T6	1120	1	0	0
T15	1624	1	0	0
T16	1469	1	0	0
T17	6206	1	0	0
T21	3482	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	258648079	4452	0	0
T1	108080	0	0	0
T2	411151	103	0	0
T3	220048	45	0	0
T5	991	13	0	0
T6	1120	0	0	0
T8	295030	24	0	0
T9	0	15	0	0
T15	1624	0	0	0
T16	1469	0	0	0
T17	6206	0	0	0
T20	0	10	0	0
T21	3482	0	0	0
T27	0	1	0	0
T35	0	2	0	0
T64	0	8	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	129323556	5963	0	0
CgEnOn_A	129323556	4289	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129323556	5963	0	0
T1	54040	1	0	0
T2	205574	118	0	0
T3	110022	48	0	0
T4	4766	1	0	0
T5	496	17	0	0
T6	559	1	0	0
T15	812	1	0	0
T16	734	1	0	0
T17	3103	1	0	0
T21	1741	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129323556	4289	0	0
T1	54040	0	0	0
T2	205574	107	0	0
T3	110022	44	0	0
T5	496	16	0	0
T6	559	0	0	0
T8	147514	26	0	0
T9	0	9	0	0
T15	812	0	0	0
T16	734	0	0	0
T17	3103	0	0	0
T20	0	11	0	0
T21	1741	0	0	0
T27	0	1	0	0
T35	0	2	0	0
T64	0	6	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	518222652	6263	0	0
CgEnOn_A	518222652	4585	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518222652	6263	0	0
T1	216225	1	0	0
T2	823049	116	0	0
T3	433033	47	0	0
T4	17485	1	0	0
T5	2007	16	0	0
T6	2235	1	0	0
T15	3189	1	0	0
T16	2894	1	0	0
T17	12465	1	0	0
T21	6984	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518222652	4585	0	0
T1	216225	0	0	0
T2	823049	105	0	0
T3	433033	43	0	0
T5	2007	15	0	0
T6	2235	0	0	0
T8	589918	26	0	0
T9	0	15	0	0
T15	3189	0	0	0
T16	2894	0	0	0
T17	12465	0	0	0
T20	0	9	0	0
T21	6984	0	0	0
T27	0	1	0	0
T35	0	2	0	0
T64	0	8	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	263673344	6085	0	0
CgEnOn_A	263673344	4411	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263673344	6085	0	0
T1	108117	1	0	0
T2	418168	115	0	0
T3	216527	43	0	0
T4	8743	1	0	0
T5	1004	15	0	0
T6	1117	1	0	0
T15	1594	1	0	0
T16	1447	1	0	0
T17	6233	1	0	0
T21	3491	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263673344	4411	0	0
T1	108117	0	0	0
T2	418168	104	0	0
T3	216527	39	0	0
T5	1004	14	0	0
T6	1117	0	0	0
T8	332413	27	0	0
T9	0	14	0	0
T15	1594	0	0	0
T16	1447	0	0	0
T17	6233	0	0	0
T20	0	11	0	0
T21	3491	0	0	0
T27	0	1	0	0
T36	0	5	0	0
T64	0	8	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T17
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	549107635	3230	0	0
CgEnOn_A	549107635	3232	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107635	3230	0	0
T2	867570	61	0	0
T3	451090	8	0	0
T8	710519	1	0	0
T16	3015	0	0	0
T17	12985	5	0	0
T18	11513	9	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	24	0	0
T35	0	2	0	0
T64	1729	0	0	0
T65	6017	7	0	0
T96	0	1	0	0
T97	0	13	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107635	3232	0	0
T2	867570	61	0	0
T3	451090	8	0	0
T8	710519	1	0	0
T16	3015	0	0	0
T17	12985	5	0	0
T18	11513	9	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	24	0	0
T35	0	2	0	0
T64	1729	0	0	0
T65	6017	7	0	0
T96	0	1	0	0
T97	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T17
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	549107635	3239	0	0
CgEnOn_A	549107635	3240	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107635	3239	0	0
T2	867570	67	0	0
T3	451090	8	0	0
T8	710519	1	0	0
T16	3015	0	0	0
T17	12985	3	0	0
T18	11513	5	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	26	0	0
T35	0	2	0	0
T64	1729	0	0	0
T65	6017	7	0	0
T96	0	1	0	0
T97	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107635	3240	0	0
T2	867570	67	0	0
T3	451090	8	0	0
T8	710519	1	0	0
T16	3015	0	0	0
T17	12985	3	0	0
T18	11513	5	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	26	0	0
T35	0	2	0	0
T64	1729	0	0	0
T65	6017	7	0	0
T96	0	1	0	0
T97	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T17
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	549107635	3282	0	0
CgEnOn_A	549107635	3285	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107635	3282	0	0
T2	867570	50	0	0
T3	451090	9	0	0
T8	710519	3	0	0
T16	3015	0	0	0
T17	12985	7	0	0
T18	11513	8	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	25	0	0
T35	0	2	0	0
T64	1729	0	0	0
T65	6017	8	0	0
T96	0	1	0	0
T97	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107635	3285	0	0
T2	867570	50	0	0
T3	451090	9	0	0
T8	710519	3	0	0
T16	3015	0	0	0
T17	12985	7	0	0
T18	11513	8	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	25	0	0
T35	0	2	0	0
T64	1729	0	0	0
T65	6017	8	0	0
T96	0	1	0	0
T97	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T17
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	549107635	3261	0	0
CgEnOn_A	549107635	3263	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107635	3261	0	0
T2	867570	60	0	0
T3	451090	7	0	0
T8	710519	2	0	0
T16	3015	0	0	0
T17	12985	5	0	0
T18	11513	7	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	25	0	0
T35	0	2	0	0
T64	1729	0	0	0
T65	6017	4	0	0
T96	0	1	0	0
T97	0	13	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549107635	3263	0	0
T2	867570	60	0	0
T3	451090	7	0	0
T8	710519	2	0	0
T16	3015	0	0	0
T17	12985	5	0	0
T18	11513	7	0	0
T19	5117	0	0	0
T20	4554	0	0	0
T27	0	25	0	0
T35	0	2	0	0
T64	1729	0	0	0
T65	6017	4	0	0
T96	0	1	0	0
T97	0	13	0	0