Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T3
0	1	Covered	T5,T2,T3
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T3
1	0	Covered	T35,T36,T37
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1169868952	11732	0	0
GateOpen_A	1169868952	11725	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1169868952	11732	0	0
T1	486463	0	0	0
T2	1857942	255	0	0
T3	979631	87	0	0
T5	4500	36	0	0
T6	5035	0	0	0
T8	1364876	52	0	0
T9	0	40	0	0
T15	7219	0	0	0
T16	6546	0	0	0
T17	28010	0	0	0
T20	0	22	0	0
T21	15700	0	0	0
T27	0	4	0	0
T35	0	6	0	0
T36	0	5	0	0
T64	0	19	0	0
T96	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1169868952	11725	0	0
T1	486463	0	0	0
T2	1857942	255	0	0
T3	979631	87	0	0
T5	4500	36	0	0
T6	5035	0	0	0
T8	1364876	52	0	0
T9	0	40	0	0
T15	7219	0	0	0
T16	6546	0	0	0
T17	28010	0	0	0
T20	0	22	0	0
T21	15700	0	0	0
T27	0	4	0	0
T35	0	6	0	0
T36	0	5	0	0
T64	0	19	0	0
T96	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T3
0	1	Covered	T5,T2,T3
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T3
1	0	Covered	T35,T36,T37
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	129323886	2888	0	0
GateOpen_A	129323886	2887	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129323886	2888	0	0
T1	54040	0	0	0
T2	205574	65	0	0
T3	110023	25	0	0
T5	496	10	0	0
T6	560	0	0	0
T8	147514	13	0	0
T9	0	11	0	0
T15	812	0	0	0
T16	734	0	0	0
T17	3104	0	0	0
T20	0	5	0	0
T21	1742	0	0	0
T27	0	1	0	0
T35	0	2	0	0
T64	0	5	0	0
T96	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129323886	2887	0	0
T1	54040	0	0	0
T2	205574	65	0	0
T3	110023	25	0	0
T5	496	10	0	0
T6	560	0	0	0
T8	147514	13	0	0
T9	0	11	0	0
T15	812	0	0	0
T16	734	0	0	0
T17	3104	0	0	0
T20	0	5	0	0
T21	1742	0	0	0
T27	0	1	0	0
T35	0	2	0	0
T64	0	5	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T3
0	1	Covered	T5,T2,T3
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T3
1	0	Covered	T35,T36,T37
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	258648403	2937	0	0
GateOpen_A	258648403	2936	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	258648403	2937	0	0
T1	108080	0	0	0
T2	411151	65	0	0
T3	220048	19	0	0
T5	992	9	0	0
T6	1121	0	0	0
T8	295031	12	0	0
T9	0	10	0	0
T15	1624	0	0	0
T16	1469	0	0	0
T17	6207	0	0	0
T20	0	5	0	0
T21	3482	0	0	0
T27	0	1	0	0
T35	0	2	0	0
T64	0	4	0	0
T96	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	258648403	2936	0	0
T1	108080	0	0	0
T2	411151	65	0	0
T3	220048	19	0	0
T5	992	9	0	0
T6	1121	0	0	0
T8	295031	12	0	0
T9	0	10	0	0
T15	1624	0	0	0
T16	1469	0	0	0
T17	6207	0	0	0
T20	0	5	0	0
T21	3482	0	0	0
T27	0	1	0	0
T35	0	2	0	0
T64	0	4	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T3
0	1	Covered	T5,T2,T3
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T3
1	0	Covered	T35,T36,T37
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	518222984	2972	0	0
GateOpen_A	518222984	2971	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518222984	2972	0	0
T1	216225	0	0	0
T2	823049	63	0	0
T3	433033	22	0	0
T5	2008	9	0	0
T6	2236	0	0	0
T8	589918	12	0	0
T9	0	10	0	0
T15	3189	0	0	0
T16	2895	0	0	0
T17	12466	0	0	0
T20	0	5	0	0
T21	6984	0	0	0
T27	0	1	0	0
T35	0	2	0	0
T64	0	5	0	0
T96	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518222984	2971	0	0
T1	216225	0	0	0
T2	823049	63	0	0
T3	433033	22	0	0
T5	2008	9	0	0
T6	2236	0	0	0
T8	589918	12	0	0
T9	0	10	0	0
T15	3189	0	0	0
T16	2895	0	0	0
T17	12466	0	0	0
T20	0	5	0	0
T21	6984	0	0	0
T27	0	1	0	0
T35	0	2	0	0
T64	0	5	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T3
0	1	Covered	T5,T2,T3
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T3
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	263673679	2935	0	0
GateOpen_A	263673679	2931	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263673679	2935	0	0
T1	108118	0	0	0
T2	418168	62	0	0
T3	216527	21	0	0
T5	1004	8	0	0
T6	1118	0	0	0
T8	332413	15	0	0
T9	0	9	0	0
T15	1594	0	0	0
T16	1448	0	0	0
T17	6233	0	0	0
T20	0	7	0	0
T21	3492	0	0	0
T27	0	1	0	0
T36	0	5	0	0
T64	0	5	0	0
T96	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263673679	2931	0	0
T1	108118	0	0	0
T2	418168	62	0	0
T3	216527	21	0	0
T5	1004	8	0	0
T6	1118	0	0	0
T8	332413	15	0	0
T9	0	9	0	0
T15	1594	0	0	0
T16	1448	0	0	0
T17	6233	0	0	0
T20	0	7	0	0
T21	3492	0	0	0
T27	0	1	0	0
T36	0	5	0	0
T64	0	5	0	0
T96	0	1	0	0