Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	627360	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3722895

1

T1

91

T6

15

T4

113

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1068677	1			T1	25		T6	20		T4	120
values[0x0]	1504906	1			T1	81		T6	8		T4	66
values[0x1]	1776672	1			T1	68		T6	7		T4	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	340390	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4009865

1

T1

113

T6

16

T4

133

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16962	1			T1	2		T47	4		T48	4
valid_sources[0x01]	17281	1			T1	1		T47	5		T48	1
valid_sources[0x02]	16848	1			T47	2		T65	3		T70	3
valid_sources[0x03]	16414	1			T1	4		T4	1		T36	32
valid_sources[0x04]	17152	1			T33	1		T36	22		T48	6
valid_sources[0x05]	17781	1			T6	1		T67	1		T48	1
valid_sources[0x06]	16834	1			T33	3		T46	28		T67	1
valid_sources[0x07]	17901	1			T1	2		T6	2		T33	1
valid_sources[0x08]	16877	1			T33	1		T67	1		T65	1
valid_sources[0x09]	17038	1			T1	4		T33	1		T46	34
valid_sources[0x0a]	17918	1			T46	8		T48	4		T70	2
valid_sources[0x0b]	16601	1			T33	4		T46	12		T67	2
valid_sources[0x0c]	15544	1			T6	1		T33	1		T36	1
valid_sources[0x0d]	15974	1			T1	4		T6	1		T4	1
valid_sources[0x0e]	15765	1			T33	4		T36	27		T46	34
valid_sources[0x0f]	16619	1			T4	2		T48	4		T65	1
valid_sources[0x10]	15790	1			T48	3		T66	1		T82	2
valid_sources[0x11]	16768	1			T1	4		T4	3		T33	8
valid_sources[0x12]	16856	1			T1	1		T33	2		T46	9
valid_sources[0x13]	16401	1			T1	1		T4	8		T33	3
valid_sources[0x14]	16948	1			T4	19		T36	26		T46	5
valid_sources[0x15]	16184	1			T33	2		T48	3		T65	2
valid_sources[0x16]	16736	1			T1	1		T33	1		T47	7
valid_sources[0x17]	17692	1			T4	2		T48	2		T65	1
valid_sources[0x18]	17479	1			T33	1		T36	17		T67	1
valid_sources[0x19]	16981	1			T4	1		T33	6		T46	16
valid_sources[0x1a]	18579	1			T47	8		T65	1		T66	1
valid_sources[0x1b]	17082	1			T6	1		T33	1		T46	15
valid_sources[0x1c]	17558	1			T1	2		T33	1		T47	4
valid_sources[0x1d]	17120	1			T6	1		T36	11		T47	3
valid_sources[0x1e]	16723	1			T1	6		T33	3		T46	21
valid_sources[0x1f]	16408	1			T33	1		T47	1		T48	2
valid_sources[0x20]	16353	1			T4	3		T36	42		T47	2
valid_sources[0x21]	17578	1			T67	3		T48	1		T65	1
valid_sources[0x22]	17549	1			T4	3		T33	2		T35	11
valid_sources[0x23]	17890	1			T1	3		T47	3		T48	2
valid_sources[0x24]	17111	1			T4	1		T33	1		T47	4
valid_sources[0x25]	17062	1			T47	2		T48	1		T65	2
valid_sources[0x26]	16745	1			T6	1		T46	6		T47	2
valid_sources[0x27]	17416	1			T1	1		T33	2		T46	7
valid_sources[0x28]	17006	1			T6	1		T33	2		T35	81
valid_sources[0x29]	16595	1			T1	4		T33	2		T36	29
valid_sources[0x2a]	16739	1			T1	1		T4	1		T33	3
valid_sources[0x2b]	16647	1			T6	1		T4	4		T33	7
valid_sources[0x2c]	17431	1			T1	2		T4	2		T47	2
valid_sources[0x2d]	18069	1			T1	2		T67	1		T70	3
valid_sources[0x2e]	16252	1			T47	6		T67	1		T48	3
valid_sources[0x2f]	15839	1			T1	1		T4	1		T36	4
valid_sources[0x30]	16546	1			T33	1		T47	5		T67	8
valid_sources[0x31]	16303	1			T4	1		T46	5		T47	1
valid_sources[0x32]	17347	1			T1	7		T4	5		T33	1
valid_sources[0x33]	16216	1			T4	1		T48	3		T65	2
valid_sources[0x34]	16190	1			T33	1		T48	5		T65	1
valid_sources[0x35]	17021	1			T46	12		T47	6		T67	2
valid_sources[0x36]	15906	1			T6	1		T4	3		T33	1
valid_sources[0x37]	16561	1			T6	1		T33	1		T70	1
valid_sources[0x38]	17221	1			T1	2		T6	1		T33	2
valid_sources[0x39]	17423	1			T4	1		T33	2		T47	1
valid_sources[0x3a]	20733	1			T33	2		T36	23		T67	3
valid_sources[0x3b]	16975	1			T1	1		T47	4		T48	1
valid_sources[0x3c]	17257	1			T47	5		T67	3		T48	2
valid_sources[0x3d]	15824	1			T6	1		T33	1		T47	3
valid_sources[0x3e]	18478	1			T36	5		T48	2		T65	6
valid_sources[0x3f]	16592	1			T4	9		T33	1		T47	3
valid_sources[0x40]	17519	1			T1	1		T33	2		T47	1
valid_sources[0x41]	16628	1			T33	1		T47	3		T48	4
valid_sources[0x42]	15992	1			T33	2		T36	19		T46	9
valid_sources[0x43]	16061	1			T4	4		T36	8		T47	5
valid_sources[0x44]	16249	1			T33	1		T36	1		T47	2
valid_sources[0x45]	17598	1			T6	1		T47	10		T67	1
valid_sources[0x46]	17229	1			T4	1		T33	2		T48	4
valid_sources[0x47]	16976	1			T1	4		T33	7		T67	1
valid_sources[0x48]	15991	1			T33	3		T67	2		T48	2
valid_sources[0x49]	17885	1			T33	2		T67	4		T48	2
valid_sources[0x4a]	17229	1			T1	4		T36	1		T48	2
valid_sources[0x4b]	17523	1			T33	1		T36	1		T47	2
valid_sources[0x4c]	16361	1			T1	3		T4	4		T33	1
valid_sources[0x4d]	16808	1			T33	1		T36	2		T67	1
valid_sources[0x4e]	16909	1			T47	3		T67	2		T48	3
valid_sources[0x4f]	17904	1			T33	7		T47	6		T67	2
valid_sources[0x50]	17200	1			T4	1		T67	2		T48	1
valid_sources[0x51]	17156	1			T33	2		T46	7		T47	1
valid_sources[0x52]	16550	1			T1	4		T6	1		T67	1
valid_sources[0x53]	15997	1			T4	5		T47	1		T67	1
valid_sources[0x54]	15732	1			T33	6		T67	1		T48	3
valid_sources[0x55]	17397	1			T33	1		T46	17		T47	12
valid_sources[0x56]	16844	1			T33	1		T47	4		T67	1
valid_sources[0x57]	17852	1			T6	2		T4	1		T33	1
valid_sources[0x58]	16821	1			T1	2		T65	2		T70	1
valid_sources[0x59]	16734	1			T33	5		T47	2		T72	2
valid_sources[0x5a]	16407	1			T4	1		T67	1		T48	2
valid_sources[0x5b]	15385	1			T6	1		T67	2		T48	1
valid_sources[0x5c]	17378	1			T47	5		T67	3		T48	1
valid_sources[0x5d]	16589	1			T6	1		T48	1		T65	2
valid_sources[0x5e]	17093	1			T1	2		T33	2		T36	2
valid_sources[0x5f]	17568	1			T1	1		T67	1		T48	2
valid_sources[0x60]	16957	1			T47	10		T48	2		T65	1
valid_sources[0x61]	16355	1			T1	2		T36	8		T46	3
valid_sources[0x62]	15755	1			T1	1		T46	9		T47	3
valid_sources[0x63]	16506	1			T4	1		T48	2		T65	3
valid_sources[0x64]	17104	1			T6	1		T4	1		T38	11
valid_sources[0x65]	17244	1			T33	1		T46	2		T67	2
valid_sources[0x66]	17500	1			T33	1		T47	3		T67	3
valid_sources[0x67]	16831	1			T33	2		T36	27		T67	1
valid_sources[0x68]	15755	1			T6	1		T46	11		T47	4
valid_sources[0x69]	15727	1			T33	2		T46	8		T47	5
valid_sources[0x6a]	16367	1			T4	2		T33	3		T47	2
valid_sources[0x6b]	16016	1			T65	2		T66	1		T72	1
valid_sources[0x6c]	16757	1			T33	2		T47	4		T67	1
valid_sources[0x6d]	18275	1			T33	2		T46	2		T47	2
valid_sources[0x6e]	17343	1			T48	3		T70	2		T72	2
valid_sources[0x6f]	18106	1			T33	2		T67	3		T48	5
valid_sources[0x70]	17150	1			T1	7		T4	2		T33	4
valid_sources[0x71]	15296	1			T4	3		T33	1		T48	2
valid_sources[0x72]	16636	1			T4	2		T33	2		T48	4
valid_sources[0x73]	17532	1			T4	1		T33	2		T67	3
valid_sources[0x74]	18077	1			T1	2		T4	4		T33	1
valid_sources[0x75]	17463	1			T33	6		T47	5		T48	1
valid_sources[0x76]	15791	1			T1	2		T4	4		T47	11
valid_sources[0x77]	16134	1			T6	1		T4	3		T33	2
valid_sources[0x78]	18335	1			T47	1		T48	1		T65	2
valid_sources[0x79]	17033	1			T48	3		T65	2		T66	1
valid_sources[0x7a]	16634	1			T33	1		T47	1		T48	2
valid_sources[0x7b]	17413	1			T1	1		T6	1		T46	6
valid_sources[0x7c]	16845	1			T1	1		T4	1		T33	2
valid_sources[0x7d]	16747	1			T4	4		T33	7		T36	1
valid_sources[0x7e]	16786	1			T4	5		T33	3		T67	5
valid_sources[0x7f]	16771	1			T4	1		T67	3		T48	4
valid_sources[0x80]	16931	1			T47	6		T67	1		T48	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

940095

1

T1

12

T6

12

T4

56

values[0x0]

all_enables

biggest_size

1413131

1

T1

51

T6

3

T4

38

values[0x1]

all_enables

biggest_size

1369669

1

T1

28

T4

19

T33

112