Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	797393855	69948	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797393855	69948	0	0
T1	379355	179	0	0
T2	765860	394	0	0
T3	1980770	1602	0	0
T4	51430	0	0	0
T6	7265	0	0	0
T9	0	198	0	0
T10	0	1609	0	0
T11	0	148	0	0
T12	0	148	0	0
T13	0	136	0	0
T14	0	1235	0	0
T15	0	176	0	0
T16	7225	0	0	0
T17	5860	0	0	0
T18	14690	0	0	0
T19	9860	0	0	0
T20	7885	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159478771	10295	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159478771	10295	0	0
T1	75871	23	0	0
T2	153172	62	0	0
T3	396154	203	0	0
T4	10286	0	0	0
T6	1453	0	0	0
T9	0	28	0	0
T10	0	213	0	0
T11	0	24	0	0
T12	0	25	0	0
T13	0	19	0	0
T14	0	196	0	0
T15	0	28	0	0
T16	1445	0	0	0
T17	1172	0	0	0
T18	2938	0	0	0
T19	1972	0	0	0
T20	1577	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159478771	14043	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159478771	14043	0	0
T1	75871	35	0	0
T2	153172	80	0	0
T3	396154	321	0	0
T4	10286	0	0	0
T6	1453	0	0	0
T9	0	40	0	0
T10	0	323	0	0
T11	0	30	0	0
T12	0	30	0	0
T13	0	27	0	0
T14	0	254	0	0
T15	0	37	0	0
T16	1445	0	0	0
T17	1172	0	0	0
T18	2938	0	0	0
T19	1972	0	0	0
T20	1577	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159478771	21401	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159478771	21401	0	0
T1	75871	61	0	0
T2	153172	110	0	0
T3	396154	529	0	0
T4	10286	0	0	0
T6	1453	0	0	0
T9	0	63	0	0
T10	0	540	0	0
T11	0	40	0	0
T12	0	41	0	0
T13	0	43	0	0
T14	0	341	0	0
T15	0	47	0	0
T16	1445	0	0	0
T17	1172	0	0	0
T18	2938	0	0	0
T19	1972	0	0	0
T20	1577	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159478771	10142	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159478771	10142	0	0
T1	75871	23	0	0
T2	153172	64	0	0
T3	396154	231	0	0
T4	10286	0	0	0
T6	1453	0	0	0
T9	0	28	0	0
T10	0	208	0	0
T11	0	24	0	0
T12	0	23	0	0
T13	0	19	0	0
T14	0	195	0	0
T15	0	29	0	0
T16	1445	0	0	0
T17	1172	0	0	0
T18	2938	0	0	0
T19	1972	0	0	0
T20	1577	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159478771	14067	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159478771	14067	0	0
T1	75871	37	0	0
T2	153172	78	0	0
T3	396154	318	0	0
T4	10286	0	0	0
T6	1453	0	0	0
T9	0	39	0	0
T10	0	325	0	0
T11	0	30	0	0
T12	0	29	0	0
T13	0	28	0	0
T14	0	249	0	0
T15	0	35	0	0
T16	1445	0	0	0
T17	1172	0	0	0
T18	2938	0	0	0
T19	1972	0	0	0
T20	1577	0	0	0