Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T4,T2,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	159478771	156734210	0	0
AllClkBypReqTrue_A	159478771	125401	0	0
IoClkBypReqFalse_A	159478771	156657703	0	2412
IoClkBypReqTrue_A	159478771	197122	0	0
LcClkBypAckFalse_A	159478771	156744610	0	0
LcClkBypAckTrue_A	159478771	115001	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159478771	156734210	0	0
T1	75871	75641	0	0
T2	153172	152670	0	0
T3	396154	392796	0	0
T4	10286	2300	0	0
T5	1196	1114	0	0
T6	1453	1412	0	0
T16	1445	1263	0	0
T17	1172	1030	0	0
T18	2938	2848	0	0
T21	1200	1101	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159478771	125401	0	0
T2	153172	1545	0	0
T3	396154	4626	0	0
T16	1445	0	0	0
T17	1172	0	0	0
T18	2938	0	0	0
T19	1972	7	0	0
T20	1577	0	0	0
T21	1200	64	0	0
T26	1895	177	0	0
T27	2320	0	0	0
T32	0	27	0	0
T100	0	4	0	0
T101	0	32	0	0
T102	0	55	0	0
T103	0	38	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159478771	156657703	0	2412
T1	75871	75639	0	3
T2	153172	152599	0	3
T3	396154	392627	0	3
T4	10286	2288	0	3
T5	1196	1112	0	3
T6	1453	1410	0	3
T16	1445	1189	0	3
T17	1172	1028	0	3
T18	2938	2846	0	3
T21	1200	1074	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159478771	197122	0	0
T2	153172	2240	0	0
T3	396154	6295	0	0
T16	1445	72	0	0
T17	1172	0	0	0
T18	2938	0	0	0
T19	1972	249	0	0
T20	1577	0	0	0
T21	1200	89	0	0
T26	1895	232	0	0
T27	2320	0	0	0
T100	0	201	0	0
T102	0	87	0	0
T103	0	195	0	0
T104	0	351	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159478771	156744610	0	0
T1	75871	75641	0	0
T2	153172	152680	0	0
T3	396154	392820	0	0
T4	10286	2300	0	0
T5	1196	1114	0	0
T6	1453	1412	0	0
T16	1445	1262	0	0
T17	1172	1030	0	0
T18	2938	2848	0	0
T21	1200	1119	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159478771	115001	0	0
T2	153172	1441	0	0
T3	396154	4389	0	0
T16	1445	1	0	0
T17	1172	0	0	0
T18	2938	0	0	0
T19	1972	94	0	0
T20	1577	0	0	0
T21	1200	46	0	0
T26	1895	123	0	0
T27	2320	0	0	0
T100	0	60	0	0
T102	0	35	0	0
T103	0	145	0	0
T104	0	78	0	0