Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1674894704	15432	0	0
TransStop_A	1674894704	7784	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1674894704	15432	0	0
T2	2088736	194	0	0
T3	1572616	237	0	0
T4	158256	0	0	0
T6	24240	14	0	0
T16	5840	0	0	0
T17	9384	0	0	0
T18	23984	29	0	0
T19	15784	0	0	0
T20	26300	16	0	0
T26	7584	0	0	0
T27	0	4	0	0
T28	0	12	0	0
T32	0	120	0	0
T105	0	4	0	0
T106	0	37	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1674894704	7784	0	0
T2	2088736	85	0	0
T3	1572616	101	0	0
T4	118692	0	0	0
T6	18180	6	0	0
T10	0	28	0	0
T16	5840	0	0	0
T17	9384	0	0	0
T18	23984	15	0	0
T19	15784	0	0	0
T20	26300	4	0	0
T26	7584	0	0	0
T27	2392	4	0	0
T28	2574	5	0	0
T32	0	57	0	0
T105	0	4	0	0
T106	0	20	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	418723676	3898	0	0
TransStop_A	418723676	1974	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723676	3898	0	0
T2	522184	43	0	0
T3	393154	65	0	0
T4	39564	0	0	0
T6	6060	4	0	0
T16	1460	0	0	0
T17	2346	0	0	0
T18	5996	9	0	0
T19	3946	0	0	0
T20	6575	4	0	0
T26	1896	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T32	0	30	0	0
T105	0	1	0	0
T106	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723676	1974	0	0
T2	522184	17	0	0
T3	393154	29	0	0
T4	39564	0	0	0
T6	6060	2	0	0
T16	1460	0	0	0
T17	2346	0	0	0
T18	5996	5	0	0
T19	3946	0	0	0
T20	6575	1	0	0
T26	1896	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T32	0	15	0	0
T105	0	1	0	0
T106	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	418723676	3839	0	0
TransStop_A	418723676	1911	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723676	3839	0	0
T2	522184	51	0	0
T3	393154	52	0	0
T4	39564	0	0	0
T6	6060	2	0	0
T16	1460	0	0	0
T17	2346	0	0	0
T18	5996	5	0	0
T19	3946	0	0	0
T20	6575	4	0	0
T26	1896	0	0	0
T27	0	1	0	0
T28	0	4	0	0
T32	0	34	0	0
T105	0	1	0	0
T106	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723676	1911	0	0
T2	522184	21	0	0
T3	393154	23	0	0
T10	0	13	0	0
T16	1460	0	0	0
T17	2346	0	0	0
T18	5996	2	0	0
T19	3946	0	0	0
T20	6575	1	0	0
T26	1896	0	0	0
T27	2392	1	0	0
T28	2574	2	0	0
T32	0	16	0	0
T105	0	1	0	0
T106	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	418723676	3904	0	0
TransStop_A	418723676	1996	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723676	3904	0	0
T2	522184	48	0	0
T3	393154	65	0	0
T4	39564	0	0	0
T6	6060	4	0	0
T16	1460	0	0	0
T17	2346	0	0	0
T18	5996	7	0	0
T19	3946	0	0	0
T20	6575	5	0	0
T26	1896	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T32	0	25	0	0
T105	0	1	0	0
T106	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723676	1996	0	0
T2	522184	23	0	0
T3	393154	27	0	0
T4	39564	0	0	0
T6	6060	2	0	0
T10	0	15	0	0
T16	1460	0	0	0
T17	2346	0	0	0
T18	5996	4	0	0
T19	3946	0	0	0
T20	6575	1	0	0
T26	1896	0	0	0
T27	0	1	0	0
T32	0	13	0	0
T105	0	1	0	0
T106	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	418723676	3791	0	0
TransStop_A	418723676	1903	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723676	3791	0	0
T2	522184	52	0	0
T3	393154	55	0	0
T4	39564	0	0	0
T6	6060	4	0	0
T16	1460	0	0	0
T17	2346	0	0	0
T18	5996	8	0	0
T19	3946	0	0	0
T20	6575	3	0	0
T26	1896	0	0	0
T27	0	1	0	0
T28	0	4	0	0
T32	0	31	0	0
T105	0	1	0	0
T106	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723676	1903	0	0
T2	522184	24	0	0
T3	393154	22	0	0
T4	39564	0	0	0
T6	6060	2	0	0
T16	1460	0	0	0
T17	2346	0	0	0
T18	5996	4	0	0
T19	3946	0	0	0
T20	6575	1	0	0
T26	1896	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T32	0	13	0	0
T105	0	1	0	0
T106	0	5	0	0