Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_extclk_ctrl

Module Instance : tb.dut.u_reg.u_extclk_ctrl_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00

Module Instance : tb.dut.u_reg.u_extclk_ctrl_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_jitter_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00

Module Instance : tb.dut.u_reg.u_jitter_enable

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_clk_enables_clk_io_peri_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_clk_enables_clk_usb_peri_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_clk_hints_clk_main_aes_hint

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	77.78	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	77.78	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	77.78	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	77.78	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.u_reg.u_measure_ctrl_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_meas_ctrl_shadowed_hi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.shadow_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_meas_ctrl_shadowed_hi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.committed_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_meas_ctrl_shadowed_hi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.staged_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_meas_ctrl_shadowed_lo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.shadow_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_meas_ctrl_shadowed_lo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.committed_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_meas_ctrl_shadowed_lo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.staged_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_div2_meas_ctrl_shadowed_hi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.shadow_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_div2_meas_ctrl_shadowed_hi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.committed_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_div2_meas_ctrl_shadowed_hi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.staged_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_div2_meas_ctrl_shadowed_lo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.shadow_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_div2_meas_ctrl_shadowed_lo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.committed_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_div2_meas_ctrl_shadowed_lo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.staged_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_div4_meas_ctrl_shadowed_hi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.shadow_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_div4_meas_ctrl_shadowed_hi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.committed_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_div4_meas_ctrl_shadowed_hi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.staged_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_div4_meas_ctrl_shadowed_lo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.shadow_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_div4_meas_ctrl_shadowed_lo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.committed_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_io_div4_meas_ctrl_shadowed_lo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.staged_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_main_meas_ctrl_shadowed_hi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.shadow_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_main_meas_ctrl_shadowed_hi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.committed_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_main_meas_ctrl_shadowed_hi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.staged_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	96.15			100.00	100.00	u_main_meas_ctrl_shadowed_lo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Line Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_regwen

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_regwen

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T35,T46

Branch Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_regwen

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T35,T46
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T4,T35,T46
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_sel

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_sel

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T21,T2

Branch Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_sel

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T21,T2
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T4,T21,T2
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T21,T2

Branch Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T21,T2
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T4,T21,T2
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_jitter_regwen

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_jitter_regwen

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T46,T48,T81

Branch Coverage for Instance : tb.dut.u_reg.u_jitter_regwen

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T46,T48,T81
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T46,T48,T81
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_jitter_enable

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_jitter_enable

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T46,T48,T81

Branch Coverage for Instance : tb.dut.u_reg.u_jitter_enable

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T46,T48,T81
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T46,T48,T81
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T46,T48,T81

Branch Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T46,T48,T81
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T46,T48,T81
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T46,T48,T81

Branch Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T46,T48,T81
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T46,T48,T81
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_peri_en

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_peri_en

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T46,T48,T81

Branch Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_peri_en

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T46,T48,T81
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T46,T48,T81
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_usb_peri_en

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_usb_peri_en

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T46,T48,T81

Branch Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_usb_peri_en

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T46,T48,T81
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T46,T48,T81
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_aes_hint

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_aes_hint

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T38,T46

Branch Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_aes_hint

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T6,T38,T46
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T6,T38,T46
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T38,T46

Branch Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T6,T38,T46
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T6,T38,T46
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T38,T46

Branch Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T6,T38,T46
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T6,T38,T46
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T38,T46

Branch Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T6,T38,T46
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T6,T38,T46
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T5,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
TERNARY	64	1	1	100.00
IF	56	2	2	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T5,T1,T6
0	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T1,T6
0	1	Covered	T5,T1,T6
0	0	Excluded		VC_COV_UNR

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T5,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
TERNARY	64	1	1	100.00
IF	56	2	2	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T5,T1,T6
0	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T1,T6
0	1	Covered	T5,T1,T6
0	0	Excluded		VC_COV_UNR

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T5,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
TERNARY	64	1	1	100.00
IF	56	2	2	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T5,T1,T6
0	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T1,T6
0	1	Covered	T5,T1,T6
0	0	Excluded		VC_COV_UNR

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T5,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
TERNARY	64	1	1	100.00
IF	56	2	2	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T5,T1,T6
0	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T1,T6
0	1	Covered	T5,T1,T6
0	0	Excluded		VC_COV_UNR

Line Coverage for Instance : tb.dut.u_reg.u_measure_ctrl_regwen

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_measure_ctrl_regwen

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_measure_ctrl_regwen

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T5,T1,T6
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T2
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.shadow_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.shadow_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.shadow_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.committed_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.committed_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.committed_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.staged_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.staged_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.staged_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.shadow_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.shadow_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.shadow_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.committed_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.committed_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.committed_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T2
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.staged_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.staged_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.staged_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.shadow_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.shadow_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.shadow_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.committed_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.committed_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.committed_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.staged_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.staged_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.staged_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.shadow_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.shadow_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.shadow_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.committed_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.committed_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.committed_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T2
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.staged_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.staged_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T35

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.staged_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T35
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T35
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.shadow_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.shadow_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T35

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.shadow_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T35
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T35
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.committed_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.committed_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T35

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.committed_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T35
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T35
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.staged_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.staged_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T35

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.staged_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T35
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T35
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.shadow_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.shadow_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T35

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.shadow_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T35
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T35
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.committed_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.committed_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T35

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.committed_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T35
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T35
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T2
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.staged_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.staged_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.staged_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.shadow_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.shadow_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.shadow_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.committed_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.committed_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.committed_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.staged_reg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.staged_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T36

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.staged_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T36
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T36
0	0	Covered	T5,T1,T6