Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	159478771	19553687	0	56

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159478771	19553687	0	56
T1	75871	24064	0	1
T2	153172	29455	0	0
T3	396154	238262	0	0
T4	10286	0	0	0
T6	1453	0	0	0
T9	0	18481	0	1
T10	0	194133	0	0
T11	0	9519	0	1
T12	0	9557	0	1
T13	0	12845	0	1
T14	0	812698	0	0
T15	0	0	0	1
T16	1445	0	0	0
T17	1172	0	0	0
T18	2938	0	0	0
T19	1972	0	0	0
T20	1577	0	0	0
T23	0	812	0	1
T107	0	0	0	1
T108	0	0	0	1
T109	0	0	0	1