Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	160395305	5493300	0	0
clk_enables_rd_A	160395305	37783	0	0
clk_hints_rd_A	160395305	34823	0	0
extclk_ctrl_rd_A	160395305	41388	0	0
extclk_ctrl_regwen_rd_A	160395305	32144	0	0
jitter_enable_rd_A	160395305	46520	0	0
jitter_regwen_rd_A	160395305	36059	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160395305	5493300	0	0
T33	8059	454	0	0
T35	2172	48	0	0
T38	3224	51	0	0
T46	6869	3	0	0
T66	871	9	0	0
T67	9364	633	0	0
T68	2876	489	0	0
T73	13231	751	0	0
T74	0	69	0	0
T75	0	680	0	0
T78	727	0	0	0
T79	1355	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160395305	37783	0	0
T38	3224	4	0	0
T49	3445	12	0	0
T67	9364	18	0	0
T68	2876	0	0	0
T69	12984	69	0	0
T70	12980	50	0	0
T73	0	37	0	0
T80	0	408	0	0
T85	1165	0	0	0
T86	1752	0	0	0
T88	8955	258	0	0
T91	0	108	0	0
T120	1549	0	0	0
T126	0	5	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160395305	34823	0	0
T38	3224	14	0	0
T49	3445	5	0	0
T67	9364	9	0	0
T68	2876	0	0	0
T69	12984	64	0	0
T70	12980	53	0	0
T73	0	26	0	0
T80	0	511	0	0
T83	0	7	0	0
T85	1165	0	0	0
T86	1752	0	0	0
T88	8955	280	0	0
T91	0	114	0	0
T120	1549	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160395305	41388	0	0
T38	3224	13	0	0
T49	3445	13	0	0
T67	9364	24	0	0
T68	2876	0	0	0
T69	12984	60	0	0
T70	12980	42	0	0
T73	0	24	0	0
T85	1165	0	0	0
T86	1752	0	0	0
T88	8955	25	0	0
T120	1549	0	0	0
T126	0	8	0	0
T127	0	4	0	0
T128	0	47	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160395305	32144	0	0
T38	3224	19	0	0
T49	3445	6	0	0
T67	9364	25	0	0
T68	2876	0	0	0
T69	12984	70	0	0
T70	12980	41	0	0
T73	0	28	0	0
T80	0	484	0	0
T83	0	13	0	0
T85	1165	0	0	0
T86	1752	0	0	0
T88	8955	95	0	0
T91	0	22	0	0
T120	1549	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160395305	46520	0	0
T38	3224	12	0	0
T49	3445	11	0	0
T67	9364	6	0	0
T68	2876	0	0	0
T69	12984	84	0	0
T70	12980	52	0	0
T73	0	35	0	0
T80	0	355	0	0
T83	0	3	0	0
T85	1165	0	0	0
T86	1752	0	0	0
T88	8955	121	0	0
T91	0	36	0	0
T120	1549	0	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160395305	36059	0	0
T38	3224	10	0	0
T49	3445	10	0	0
T67	9364	11	0	0
T68	2876	0	0	0
T69	12984	92	0	0
T70	12980	38	0	0
T73	0	25	0	0
T80	0	426	0	0
T83	0	5	0	0
T85	1165	0	0	0
T86	1752	0	0	0
T88	8955	113	0	0
T91	0	30	0	0
T120	1549	0	0	0